ECEN 248 Lab 4: Multiplexer Based Arithmetic Logic Unit

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Presentation transcript:

ECEN 248 Lab 4: Multiplexer Based Arithmetic Logic Unit names Dept. of Electrical and Computer Engineering

Lab 4 in Brief Design a 4-bit arithmetic logic unit which does elementary computation like: Addition Subtraction Bit-wise AND Use a multiplexer based control to choose between the operations

Unsigned Number Representation This is used for unsigned numbers (i.e., positive and negative are not defined) 3

Two’s Complement Used to represent both positive and negative (signed) integers Positive numbers are represented by their ordinary binary representation Negative numbers are represented by the two’s complement

Converting to Two’s Complement Step 1: Start with the ordinary binary representation of the number Ex: If we want to convert -3 to Two’s Complement, we start with representing 3 as 011 Step 2: Invert all the bits of the number Ex: Inverting all the bits of 011 results in 100 Step 3: Add 1 to the resulting value Ex: 100 + 1 = 101 If the addition results in an overflow, ignore it. Taking the Two’s Complement of the result will give you the positive number back! 5

Multiplexers (Mux) A device which selects a single input from a series of inputs and passes its value to the output The selection is done based on data fed to the control lines (S) of the mux 2:1 Multiplexer 4:1 Multiplexer

Arithmetic Logic Unit (ALU) Performs arithmetic and logic operations Fundamental building block of a CPU Inputs to the ALU: Two numbers (operands) Control bits to control what operation the ALU is performing Outputs of the ALU: The computed result An indication if the operation has resulted in an overflow

Arithmetic Logic Unit (ALU)

Specifics and Design Hints Components to design the ALU: One 2:1 Multiplexer block (Four 2:1 Multiplexers with same select line (C0)) One XOR Chip (Four XOR Gates) One 4-Bit Adder Block 5 LEDs to show Outputs Hints for the design of the ALU: Multiplexer Select Line Input is C0 C1 decides whether addition or Subtraction For subtraction when C1=1, use XOR gates to invert the inputs and Cin of the full adder to add ‘1’(i.e. C0) for the 2’s complement of the 2nd operand. Four bit adder block does addition and subtraction.

Deadlines Today Next Week Work on Lab 4 Lab 4 Post-Lab due Lab 5 Pre-Lab: no deliverables