Digital Logic Problems (II) Prof. Sin-Min Lee Department of Mathematics and Computer Science.

Slides:



Advertisements
Similar presentations
Digital Circuits.
Advertisements

Combinational Circuits
Functions and Functional Blocks
Prof. Sin-Min Lee Department of Computer Science
Decoders/DeMUXs CS370 – Spring Decoder: single data input, n control inputs, 2 outputs control inputs (called select S) represent Binary index of.
1 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 Programmable Configurations Read Only Memory (ROM) – –a fixed array of AND gates.
Multiplexors Sequential Circuits and Finite State Machines Prof. Sin-Min Lee Department of Computer Science.
Computer Arithmetic, Multiplexers Prof. Sin-Min Lee Department of Computer Science.
EE2174: Digital Logic and Lab
DIGITAL SYSTEMS TCE OTHER COMBINATIONAL LOGIC CIRCUITS DECODERS ENCODERS.
ECE 301 – Digital Electronics Multiplexers and Demultiplexers (Lecture #12)
Lecture 3. Boolean Algebra, Logic Gates
Multiplexer MUX. 2 Multiplexer Multiplexer (Selector)  2 n data inputs,  n control inputs,  1 output  Used to connect 2 n points to a single point.
Dewan Tanvir Ahmed SITE, UofO
Chapter2 Digital Components Dr. Bernard Chen Ph.D. University of Central Arkansas Spring 2009.
ETE Digital Electronics Multiplexers, Decoders and Encoders [Lecture:10] Instructor: Sajib Roy Lecturer, ETE, ULAB.
Combinational Logic Chapter 4.
Decoders and Multiplexers Prof. Sin-Min Lee Department of Computer Science San Jose State University.
Outline Decoder Encoder Mux. Decoder Accepts a value and decodes it Output corresponds to value of n inputs Consists of: Inputs (n) Outputs (2 n, numbered.
Combinational Logic Design
Digital Computer Concept and Practice Copyright ©2012 by Jaejin Lee Logic Circuits I.
Logic Design A Review. Binary numbers Binary numbers to decimal  Binary 2 decimal  Decimal 2 binary.
WEEK #9 FUNCTIONS OF COMBINATIONAL LOGIC (DECODERS & MUX EXPANSION)
1 © 2015 B. Wilkinson Modification date: January 1, 2015 Designing combinational circuits Logic circuits whose outputs are dependent upon the values placed.
ROM & PLA Digital Logic And Computer Design
Combinational Design, Part 3: Functional Blocks
Multiplexers and Demultiplexers, and Encoders and Decoders
CHAPTER 4 Combinational Logic
Computer Science 210 Computer Organization Control Circuits Decoders and Multiplexers.
Hamming Code,Decoders and D,T-flip flops Prof. Sin-Min Lee Department of Computer Science.
Magnitude Comparator A magnitude comparator is a combinational circuit that compares two numbers, A and B, and then determines their relative magnitudes.
1 CS 151: Digital Design Chapter 3: Combinational Logic Design 3-1Design Procedure CS 151: Digital Design.
Multiplexors Decoders  Decoders are used for forming separate signals for different combination of input signals.  The multiplexer circuit is a digital.
Digital System Design Multiplexers and Demultiplexers, and Encoders and Decoders.
Digital Design Module 2 Decoder Amit Kumar AP SCSE, GU Greater Noida.
1 DLD Lecture 16 More Multiplexers, Encoders and Decoders.
Digital Design Module 2 Multiplexer and Demultiplexer
Chapter4: Combinational Logic Part 4 Originally By Reham S. Al-Majed Imam Muhammad Bin Saud University.
CSCE 211: Digital Logic Design Chin-Tser Huang University of South Carolina.
Multiplexer.
MSI Circuits.
Gunjeet kaur Dronacharya Group of Institutions. Demultiplexers.
Digital Logic.
Prof. Sin-Min Lee Department of Computer Science
Prof. Sin-Min Lee Department of Computer Science
Computer Science 210 Computer Organization
CS221: Digital Logic Design Combinational Circuits 3
And Decoders Prof. Sin-Min Lee Department of Computer Science
And Decoders Prof. Sin-Min Lee Department of Computer Science
More Devices: Control (Making Choices)
Multiplexers and Demultiplexers,
Combinational Functions and Circuits
Lecture 4: Combinational Functions and Circuits
ECE 434 Advanced Digital System L03
Magnitude Comparator A magnitude comparator is a combinational circuit that compares two numbers, A and B, and then determines their relative magnitudes.
Computer Science 210 Computer Organization
CSCE 211: Digital Logic Design
CSCE 211: Digital Logic Design
Programmable Configurations
COE 202: Digital Logic Design Combinational Circuits Part 3
Dr. Clincy Professor of CS
CSCE 211: Digital Logic Design
13 Digital Logic Circuits.
CSCE 211: Digital Logic Design
Multiplexers For the rest of the day, we’ll study multiplexers, which are just as commonly used as the decoders we presented last time. Again, These serve.
Digital System Design Combinational Logic
Multiplexers Next, we’ll study multiplexers, which are just as commonly used as the decoders we presented last time. Again, These serve as examples for.
Chapter 2 Digital Design and Computer Architecture, 2nd Edition
ECE 352 Digital System Fundamentals
Presentation transcript:

Digital Logic Problems (II) Prof. Sin-Min Lee Department of Mathematics and Computer Science

Multiplexers A combinational circuit that selects info from one of many input lines and directs it to the output line. The selection of the input line is controlled by input variables called selection inputs. They are commonly abbreviated as “MUX”.

Implementing Boolean functions with multiplexers Any Boolean function of n variables can be implemented with 2 n -1 -to-1 multiplexer. The procedure for implementing a Boolean function with a multiplexer is 1.Express the function in its sum of minterms form. 2. Order the sequence of variables chosen for the minterms. Suppose the sequence is, where A is the leftmost variable, and are the remaining n -1 variables.

3.Connect the n -1 variables to the selection lines of the 2 n -1 -to-1 multiplexer, with B connected to the highest order selection line, and so on. 4. Construct the implementation table: List all the minterms in two rows. The first row consists of minterms 0 to 2 n (in all of which A is complemented). The second row consists of minterms 2 n -1 to 2 n -1 (in all of which A is uncomplemented)..

5. Circle all the minterms of the function and inspect each column in the implementation table separately If the two minterms in a column are not circled, apply 0 to the corresponding multiplexer input. If the two minterms are circled, apply 1 to the corresponding multiplexer input. If the bottom minterm is circled, and the top is not circled, apply A to the corresponding multiplexer input. If the top minterm is circled but not the bottom, apply A*

Multiplexers and decoders are used when many lines of information are being gated and passed from one part of a circuit to another. Multiplexing is when multiple data signals share a common propagation path. Time multiplexing is when different signals travel along the same wire but at different times. These devices have data and address lines, and usually include an enable/ disable input. When the device is disabled the output is locked into some particular state and is not effected by the inputs.

Consider the function of 3 variables: 1. Input variables B and C are applied to the selection lines s 1 and s 0, respectively. 2. Construct the implementation table, and circle all the minterms of the function in the implementation table 3. Apply 0, 1, A, and A* to the inputs I 0 through I 3.

Multiplexers (continued) S 0 and S 1 are the selection inputs. D 0, D 1, D 2, D 3 are the input lines.

Multiplexers (continued) MUX blocks can be combined in parallel with common selection and enable inputs to perform selection on multiple bit quantities.

Combinational circuit implementation using MUX We can use Multiplexers to express Boolean functions also. Expressing Boolean functions as MUXs is more efficient than as decoders. First n-1 variables of the function used as selection inputs; last variable used as data inputs. If last variable is called Z, then each data input has to be Z, Z’, 0, or 1.

Karnaugh Map Method of Multiplexer Implementation Consider the function: A is taken to be the data variable and B,C to be the select variables.

Example of MUX combo circuit F(X,Y,Z) =  m(1,2,6,7)

Implement g(w,x,y)=wx+xy+wy using a 4-1 multiplexer.