Florida International University Chapter 17 Micro-programmed Control Molina, Francisco Pineiro, Michael Romero, Rubymir

Basic Concepts Microprogrammed Control Unit: The logic of the control unit is specified by a microprogram. Microprogram: Sequence of instructions in a microprogramming language; these instructions are simple and specify micro- operations.

Basic Concepts II ◦ Each micro-operation is described by a symbolic notation, which looks like a programming language (Micro- programming Language). ◦ Each line describes a set of micro-operations (Microinstructions). ◦ A sequence of instructions is a Microprogram, or firmware.

Implementation of Control Unit Using the Concept of Microprogramming(1) All the control unit is allowed to do is to generate a set of control signals. For each micro-operation, each micro line from control unit is on or off. Represent each control signal by a binary digit (bit), or 1 and 0. Construct a control word  each bit: one control line Each micro-operation represented by different patterns of 0s and 1s in the control word.

Implementation of Control Unit Using the Concept of Microprogrmming(1I) Place control words in memory; each word with a unique address. Add address field to each control word, to indicate location of next control word to be executed under given conditions. Add a few bits to specify the condition.

Typical Microinstruction Formats

Micro-Instruction Types ◦ Vertical micro-programming Each micro-instruction specifies single (or few) micro-operations to be performed ◦ Horizontal micro-programming Each micro-instruction specifies many different micro-operations to be performed in parallel

Horizontal Micro-programming Wide memory word High degree of parallel operations possible Little encoding of control information

Vertical Micro-programming Width is narrow Limited ability to express parallelism Considerable encoding of control information requires external memory word decoder to identify the exact control line being manipulated

Control Unit Contains stored set of microinstructions Contains the address of next microinstruction When a microinstruction is read from the Control Memory, it is transferred to a Control Buffer Register Loads the control address register and issues a read command

Control Unit Function & Organization During one clock pulse Sequence logic unit issues read command to the control unit. Word specified in control address register is read into control buffer register Control buffer register contents generates control signals and next address information for the sequencing logic unit Sequence logic loads new address into control buffer register based on next address information from control buffer register and ALU flags

Advantages & Disadvantages Simplifies the design of the control unit. Cheaper and less error prone for implementation. The decoders and sequenced logic unit are very simple pieces of logic in comparison to a hardwired control unit, which has complex logic for sequencing. Slower that a hardwired unit of comparable technology.

Tasks Done By Microprogrammed Control Unit Microinstruction sequencing Microinstruction execution Must consider both together

Design Considerations Size of microinstructions Address generation time ◦ Determined by instruction register  Once per cycle, after instruction is fetched ◦ Next sequential address  Common in most designed ◦ Branches  Both conditional and unconditional

Sequencing Techniques Based on current microinstruction, condition flags, contents of IR, control memory address must be generated Based on format of address information ◦ Two address fields ◦ Single address field ◦ Variable format

Branch Control Logic: Two Address Fields This is the simplest approach, a multiplexer provides a destination for both address fields, and the IR. The next two approaches have one bit designating which format will be used.

Branch Control Logic: Single Address Field This format has the remaining bits are used to activate the Control Signal. The next address is either the next sequential address or a derived address from the IR.

Branch Control Logic: Variable Format In the second format either the conditional or unconditional branch is being specified. The disadvantage is that an entire cycle is used to each microinstruction

Address Generation ExplicitImplicit Two-fieldMapping Unconditional BranchAddition Conditional branchResidual control A conditional branch instruction depends on: ALU flags, the Opcode or address fields of the instruction, the register, and the status bits of the Control Unit.

MICROPROGRAMMED CONTROL Control Memory Sequencing Microinstructions Microprogram Example Design of Control Unit Microinstruction Format

COMPARISON OF CONTROL UNIT IMPLEMENTATIONS Implementation of Control Unit Control Unit Implementation Combinational Logic Circuits (Hard-wired) Microprogram I R Status F/Fs Control Data Combinational Logic Circuits Control Points CPU Memory Timing State Ins. Cycle State Control Unit's State Status F/Fs Control Data Next Address Generation Logic C S A R Control Storage (  -program memory) M e m o r y I R C S D R C P s CPUD }

TERMINOLOGY Microprogram - Program stored in memory that generates all the control signals required to execute the instruction set correctly - Consists of microinstructions Microinstruction - Contains a control word and a sequencing word Control Word - All the control information required for one clock cycle Sequencing Word - Information needed to decide the next microinstruction address - Vocabulary to write a microprogram Control Memory(Control Storage: CS) - Storage in the microprogrammed control unit to store the microprogram Writeable Control Memory(Writeable Control Storage:WCS) - CS whose contents can be modified -> Allows the microprogram can be changed -> Instruction set can be changed or modified Dynamic Microprogramming - Computer system whose control unit is implemented with a microprogram in WCS - Microprogram can be changed by a systems programmer or a user

TERMINOLOGY Sequencer (Microprogram Sequencer) A Microprogram Control Unit that determines the Microinstruction Address to be executed in the next clock cycle - In-line Sequencing - Branch - Conditional Branch - Subroutine - Loop - Instruction OP-code mapping

MICROINSTRUCTION SEQUENCING Sequencing Capabilities Required in a Control Storage - Incrementing of the control address register - Unconditional and conditional branches - A mapping process from the bits of the machine instruction to an address for control memory - A facility for subroutine call and return Sequencing Instruction code Mapping logic Multiplexers Control memory (ROM) Subroutine register (SBR) Branch logic Status bits Microoperations Control address register (CAR) Incrementer MUX select select a status bit Branch address

CONDITIONAL BRANCH Unconditional Branch Fixing the value of one status bit at the input of the multiplexer to 1 Sequencing Conditional Branch If Condition is true, then Branch (address from the next address field of the current microinstruction) else Fall Through Conditions to Test: O(overflow), N(negative), Z(zero), C(carry), etc. Control address register Control memory MUX Load address Increment Status (condition) bits Micro-operations Condition select Next address...

MAPPING OF INSTRUCTIONS Sequencing ADD Routine AND Routine LDA Routine STA Routine BUN Routine Control Storage OP-codes of Instructions ADD AND LDA STA BUN Direct Mapping Address Mapping Bits 10 xxxx 010 ADD Routine Address AND Routine LDA Routine STA Routine BUN Routine

MAPPING OF INSTRUCTIONS TO MICROROUTINES Mapping function implemented by ROM or PLA OP-code Mapping memory (ROM or PLA) Control address register Control Memory Mapping from the OP-code of an instruction to the address of the Microinstruction which is the starting microinstruction of its execution microprogram Address OP-code Mapping bits Microinstruction address 0 x x x x Machine Instruction Sequencing

MICROPROGRAM EXAMPLE Microprogram Computer Configuration MUX AR 100 PC 100 Address Memory 2048 x 16 MUX DR 150 Arithmetic logic and shift unit AC 15 0 SBR 60 CAR 60 Control memory 128 x 20 Control unit

MACHINE INSTRUCTION FORMAT Microinstruction Format Microprogram EA is the effective address Symbol OP-code Description ADD 0000AC  AC + M[EA] BRANCH 0001 if (AC < 0) then (PC  EA) STORE 0010M[EA]  AC EXCHANGE 0011AC  M[EA], M[EA]  AC Machine instruction format I Opcode Address 0 Sample machine instructions F1F2F3CDBRAD F1, F2, F3: Microoperation fields CD: Condition for branching BR: Branch field AD: Address field

MICROINSTRUCTION FIELD DESCRIPTIONS - F1,F2,F3 F1MicrooperationSymbol 000NoneNOP 001AC  AC + DRADD 010AC  0CLRAC 011AC  AC + 1INCAC 100AC  DRDRTAC 101AR  DR(0-10)DRTAR 110AR  PCPCTAR 111M[AR]  DRWRITE Microprogram F2MicrooperationSymbol 000NoneNOP 001AC  AC - DRSUB 010AC  AC  DROR 011AC  AC  DRAND 100DR  M[AR]READ 101DR  ACACTDR 110DR  DR + 1INCDR 111DR(0-10)  PCPCTDR F3MicrooperationSymbol 000NoneNOP 001AC  AC  DRXOR 010AC  AC’COM 011AC  shl ACSHL 100AC  shr ACSHR 101PC  PC + 1INCPC 110PC  ARARTPC 111Reserved

MICROINSTRUCTION FIELD DESCRIPTIONS - CD, BR CDCondition Symbol Comments 00Always = 1UUnconditional branch 01DR(15) IIndirect address bit 10AC(15)SSign bit of AC 11AC = 0ZZero value in AC BR Symbol Function 00 JMP CAR  AD if condition = 1 CAR  CAR + 1 if condition = 0 01 CALL CAR  AD, SBR  CAR + 1 if condition = 1 CAR  CAR + 1 if condition = 0 10 RET CAR  SBR (Return from subroutine) 11 MAP CAR(2-5)  DR(11-14), CAR(0,1,6)  0 Microprogram

SYMBOLIC MICROINSTRUCTIONS Symbols are used in microinstructions as in assembly language A symbolic microprogram can be translated into its binary equivalent by a microprogram assembler. Sample Format five fields: label; micro-ops; CD; BR; AD Label: may be empty or may specify a symbolic address terminated with a colon Micro-ops: consists of one, two, or three symbols separated by commas CD: one of {U, I, S, Z}, whereU: Unconditional Branch I: Indirect address bit S: Sign of AC Z: Zero value in AC BR: one of {JMP, CALL, RET, MAP} AD: one of {Symbolic address, NEXT, empty} Microprogram

SYMBOLIC MICROPROGRAM - FETCH ROUTINE AR    PC DR   M[AR], PC  PC + 1 AR  DR(0-10), CAR(2-5)  DR(11-14), CAR(0,1,6)  0 Symbolic microprogram for the fetch cycle: ORG 64 PCTAR U JMP NEXT READ, INCPC U JMP NEXT DRTAR U MAP FETCH: Binary equivalents translated by an assembler Binary address F1 F2 F3 CD BR AD Microprogram During FETCH, Read an instruction from memory and decode the instruction and update PC Sequence of microoperations in the fetch cycle:

SYMBOLIC MICROPROGRAM Control Storage: bit words The first 64 words: Routines for the 16 machine instructions The last 64 words: Used for other purpose (e.g., fetch routine and other subroutines) Mapping: OP-code XXXX into 0XXXX00, the first address for the 16 routines are 0( ), 4( ), 8, 12, 16, 20,..., 60 Microprogram ORG 0 NOP READ ADD ORG 4 NOP ARTPC ORG 8 NOP ACTDR WRITE ORG 12 NOP READ ACTDR, DRTAC WRITE ORG 64 PCTAR READ, INCPC DRTAR READ DRTAR I U S U I U I U I U CALL JMP CALL JMP CALL JMP CALL JMP MAP JMP RET INDRCT NEXT FETCH OVER FETCH INDRCT FETCH INDRCT NEXT FETCH INDRCT NEXT FETCH NEXT ADD: BRANCH: OVER: STORE: EXCHANGE: FETCH: INDRCT: Label Microops CD BR AD Partial Symbolic Microprogram

This microprogram can be implemented using ROM Microprogram Address Binary Microinstruction Micro Routine Decimal Binary F1 F2 F3 CD BR AD ADD BRANCH STORE EXCHANGE FETCH INDRCT BINARY MICROPROGRAM

DESIGN OF CONTROL UNIT - DECODING ALU CONTROL INFORMATION - Design of Control Unit microoperation fields 3 x 8 decoder F1 3 x 8 decoder F2 3 x 8 decoder F3 Arithmetic logic and shift unit AND ADD DRTAC AC Load From PC From DR(0-10) Select 01 Multiplexers AR Load Clock AC DR DRTAR PCTAR

HORIZONTAL AND VERTICAL MICROINSTRUCTION FORMAT Horizontal Microinstructions Each bit directly controls each micro-operation or each control point Horizontal implies a long microinstruction word Advantages: Can control a variety of components operating in parallel. --> Advantage of efficient hardware utilization Disadvantages: Control word bits are not fully utilized --> CS becomes large --> Costly Vertical Microinstructions A microinstruction format that is not horizontal Vertical implies a short microinstruction word Encoded Microinstruction fields --> Needs decoding circuits for one or two levels of decoding Microinstruction Format One-level decoding Field A 2 bits 2 x 4 Decoder 3 x 8 Decoder Field B 3 bits 1 of 4 1 of 8 Two-level decoding Field A 2 bits 2 x 4 Decoder 6 x 64 Decoder Field B 6 bits Decoder and selection logic

Review Questions 1. What is the difference between a hardwired implementation and a micro- programmed implementation of a control unit? 2. How is a horizontal microinstruction interpreted? 3. What is the purpose of the control memory? 4. What is the typical sequence in the execution of a horizontal microinstruction? 5. What is the difference between horizontal and vertical microinstruction? 6. What is the difference between functional and resource encoding? 7. List some common applications of microprogramming. 8. Where is the opcode in the address ? 9. What is the formula to calculate the number of bit need for a given number of signal controls? 10. Where is the microinstruction code store ?