1 EE121 John Wakerly Lecture #6 Three-state Outputs Encoders Multiplexers XOR gates.

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Presentation transcript:

1 EE121 John Wakerly Lecture #6 Three-state Outputs Encoders Multiplexers XOR gates

2 Three-state buffers Output = LOW, HIGH, or Hi-Z. Can tie multiple outputs together, if at most one at a time is driven.

3 Different flavors

4

5 Timing considerations

6 Three-state drivers

7 Driver application

8 Three-state transceiver

9 Transceiver application

10 Three-state enables in ABEL

11 Encoders vs. Decoders DecoderEncoder

12 Binary encoders

13 Need priority in most applications

14 8-input priority encoder

15 Priority-encoder logic equations

16 74x148 8-input priority encoder –Active-low I/O –Enable Input –“Got Something” –Enable Output

17 74x148 circuit

18 74x148 Truth Table

19 Cascading priority encoders 32-input priority encoder

20 15-input priority encoder in ABEL Declarations

21 Constant expressions

22 Outputs

23 Alternative formulation WHEN is very natural for priority function

24 Multiplexers

25 74x151 8-input multiplexer

26 74x151 truth table

27 CMOS transmission gates 2-input multiplexer

28 Other multiplexer varieties 2-input, 4-bit-wide –74x157 4-input, 2-bit-wide –74x153

29 ABEL code for 74x153-like mux

30 Easier ABEL multiplexer code

31 Barrel shifter design example n data inputs, n data outputs Control inputs specify number of positions to rotate or shift data inputs Example: n = 16 –DIN[15:0], DOUT[15:0], S[3:0] (shift amount) Many possible solutions, all based on multiplexers

to-1 muxes 16-to-1 mux = 2 x 74x151 8-to-1 mux + NAND gate

bit 2-to-1 muxes 16-bit 2-to-1 mux = 4 x 74x157 4-bit 2-to-1 mux

34 Properties of different approaches

35 ABEL code for barrel shifter 20 inputs 16 outputs 16 product terms per output

36 2-input XOR gates Like an OR gate, but excludes the case where both inputs are 1. XNOR: complement of XOR

37 XOR and XNOR symbols

38 Gate-level XOR circuits No direct realization with just a few transistors.

39 CMOS XOR with transmission gates IF B==1 THEN Z = !A; ELSE Z = A;

40 Multi-input XOR Sum modulo 2 Parity computation Used to generate and check parity bits in computer systems. –Detects any single-bit error

41 Parity tree Faster with balanced tree structure

42 Next time Comparators Adders Multipliers Read-only memories (ROMs)