Architecture and Features 9

Agenda Top-level architecture and attributes Configurable logic block Memory I/O block Three-state buses Clocks and delay-locked loops Power down mode Configuration This presentation provides an overview of the Spartan-II family architecture.

Introducing the Spartan-II FPGA The Spartan-II FPGA was introduced in January 2000.

The Leading Programmable Logic Solution for Consumer Electronics Plentiful logic and memory resources 15K to 200K system gates (up to 5,292 logic cells) Up to 57 Kb block RAM storage Flexible I/O interfaces From 86 to 284 I/Os 16 signal standards High performance System frequency as high as 200 MHz Spartan FPGAs provide the low cost and high feature content required to be used in consumer electronics applications.

Complete Solution Low power Programmable flexibility Power down mode guarantees minimum power 2.5-V core supply voltage Programmable flexibility Speeds time to market for your product Lowest cost FPGAs in the industry 100,000 system gate device for $10 The Spartan-II family has “No Compromises”, providing a complete solution at low cost. Pricing for 250,000 units, end-2000, slowest speed, cheapest package

Spartan-II Top-level Architecture Configurable logic blocks Implement logic here! I/O blocks Communicate with other chips Choose from 16 signal standards Block RAM On-chip memory for higher performance Now we will look at the details of the architecture. Each of these sections will be examined in more detail later in the presentation.

Spartan-II Top-level Architecture (cont’d) Clocks and delay-locked loops Synchronize to clock on and off chip Rich interconnect resources Three-state internal buses Power down mode Lower quiescent power

Spartan-II Family Overview The XC2S200 was recently added to extend the family to 200,000 system gates.

CLB Slice (Simplified) 1 CLB holds 2 slices Each slice contains two sets of the following: Four-input LUT Any 4-input logic function Or 16-bit x 1 RAM Or 16-bit shift register The FPGA is made up of an array of Configurable Logic Blocks (CLBs), and each CLB is made up of two slices, and each slice has two Look-Up Tables (LUTs) and 2 flip-flops.

CLB Slice (cont’d) Each slice contains two sets of the following: Carry & control Fast arithmetic logic Multiplier logic Multiplexer logic Storage element Latch or flip-flop Set and reset True or inverted inputs Sync. or async. control

Dedicated Expansion Multiplexers CLB MUXF5 combines 2 LUTs to form 4x1 multiplexer Or any 5-input function MUXF6 combines 2 slices to form 8x1 multiplexer Or any 6-input function Slice LUT MUXF6 LUT MUXF5 Slice LUT Special logic in the CLB allows logic expansion beyond just using the lookup tables. LUT MUXF5

Dedicated Multiplier Logic Highly efficient ‘shift & add’ implementation For a 16x16 multiplier 30% reduction in area 1 less logic level Parallel multiplication uses fewer resources and is faster than a serial implementation. Special logic in the CLB accommodates this.

Look-up Table Shift Registers Each LUT can be configured as shift register Serial in, serial out Dynamically addressable delay up to 16 cycles LUT IN D Q CE CE CLK D Q CE 1 D Q OUT CE 2 Each LUT can be used like 16 flip-flops in a shift register. CLB Slice Slice LUT LUT D Q CE 15 LUT LUT ADDR[3:0]

Flexible Cycle Delays Use for programmable clock delay LUT Use for programmable clock delay Cascade for greater cycle delays Use CLB flip-flops to add depth IN D Q CE CE CLK D Q CE D Q OUT CE CLB Slice Slice LUT LUT D Q CE LUT LUT ADDR[3:0]

Memory Bandwidth and Flexibility Spartan-II on-chip SelectRAM+TM memory Large FIFOs Packet Buffers Video Line Buffers Cache Tag Memory Deep/Wide SDRAM ZBTRAM SSRAM SGRAM bytes 16x1 DSP Coefficients Small FIFOs Shallow/Wide Distributed RAM 4Kx1 2Kx2 1Kx4 512x8 256x16 Three types of memory are supported - small distributed RAM in the LUTs, large block RAM, or very large external RAM. Block RAM External RAM kilobytes megabytes 200 MHz Memory Continuum Highest performance FPGA memory system

Block RAM Provides 4K Bits Each Dual read/write ports, each with: Independent clock, R/W, and enable Independently configurable data width from 4Kx1 to 256x16 W Port A Spartan-II Dual-R/W Port Block RAM Port B R Data Flow Spartan-II A to B Yes B to A Yes A to A Yes B to B Yes R W W W R R

Block RAM Timing Clock-to-output (glitch-free): 2.5 ns typ. Address/data input setup: 1.0 ns typ. Lookup table based RAM provides additional small memories (16x1) Same timing as CLB logic Both easily initialized at configuration to simulate ROM

I/O Block (Simplified) Registered input, output, 3-state control Programmable slew rate, pull-up, pull-down, keeper and input delay The I/O block features are automatically used according to the design entered into the development system.

I/O Interface Standards I/O can be programmed for 16 different signal standards VCCO controls maximum output swing VREF sets input, output, three-state control Different banks can support different standards at the same time Logic level translation Boards with mixed standards A wide variety of I/O interface standards are supported, such as HSTL, SSTL, GTL, etc.

IOBs Organized As Independent Banks As many as eight banks on a device Package dependent Each bank can be assigned any of the 16 signal standards

Spartan-II As Center for Signal Translation Chip to Chip LVTTL, LVCMOS Chip to Memory SSTL2-I, SSTL2-II, SSTL3-I, SSTL3-II, HSTL-I, HSTL-III, HSTL-IV, CTT Chip to Backplane PCI33-5V, PCI33-3.3V, GTL, GTL+, AGP SSTL SDRAM HSTL LVTTL LVCMOS CTT SRAM GTL+ No external translators are necessary when using the Spartan-II family. Allows support for future standards!

Performance Challenge Met by Spartan-II Speed Consistently high performance across I/O signal standards

Performance Challenge Met by Spartan-II Speed (cont’d) Dedicated block RAM equals ASIC performance Delay-locked loop maximizes internal & external performance

Comparison of Interface Standards Newer interface standards are compressing the noise margins, providing a much smaller signaling window.

High Performance Routing 2ns Vector Based Interconnect CLB Array Hierarchical routing Singles, hexes, longs Sparse connections on longer interconnects for high speed Routing delay depends primarily on distance Direction independent Device-size independent Predictable for early design analysis The development system automatically takes advantage of abundant routing to implement any design quickly and efficiently. Timing does not vary considerably from one implementation to the next since delays are based on distance, not direction.

Internal Three-state Buses Two 3-state drivers per CLB Permits using internal 3-state buses for a “system on a chip” OR-AND logic implementation in place of 3-state drivers Internal three-state buffers allow the creation of internal busses. In the Spartan-II family, these buffers are actually built as a multiplexer, simplifying their use.

Internal Three-state Buses (cont’d) Low power No danger of contention when multiple BUFTs enabled No physical pullups or large capacitance to drive With no drivers enabled, bus is a logic 1

General Clock Support Four dedicated global low skew buffers Dedicated input pin (clock distribution only) 66-MHz PCI with 500-ps maximum skew Input IOB flip-flop (no data delay): ts = 3 ns / th = 0 ns Output IOB flip-flop: tco = 6 ns typ. Additional shared resources (e.g., long lines) Distribute low-skew/high-fanout signals (10 ns max.) Four delay-locked loops on each device Two global buffers associated with each DLL pair All-digital implementation The most important feature for clock signals is the high-speed, low-skew clock buffers and dedicated routing. Delay-locked loops can be used to multiply, divide, phase shift, or change the duty cycle of any clock.

Delay-locked Loop Functions Eliminate clock distribution delay for fast TCO System synchronization (e.g., clock mirrors) Phase-shifted clocks Clock multiplication and division Clean up clocks with 50/50 duty cycle correction Clock lock for internal & external synchronization DLL feedback connected internally or externally Can synchronize configuration to DLL lock

DLL Macros Two DLL versions available CLKDLL (low frequency) Controlled by macro choice CLKDLL (low frequency) Input frequency: 25 MHz to 100 MHz All 6 outputs available CLK0, CLK90, CLK180, CLK270, CLK2X & CLKDV CLKDLLHF (high frequency) Input frequency 60 MHz to 200 MHz 3 outputs available CLK0, CLK180 & CLKDV

Improved Clock-to-out Using DLL Spartan-II clock-to-out delays reduced over 50% Output standard = LVTTL Fast 16mA (OBUF_F_16) Temp=room, Vdd=2.5V, Vcco=3.3V Waveforms: 1: CLKIN 2: DATA OUT (no DLL) 3: DATA OUT (DLL deskewed) Timing w/o DLL w/ DLL r->r r->f r->r r->f 3.6n 3.5n 1.4n 1.4n A key benefit of the DLL is the ability to “remove” delay from the clock path, and improve the effective clock-to-out delay.

Spartan-II DLLs Improve Clock Networks Deskew Clocks on Board DLL1 DLL2 Deskew Clocks on Chip Manage up to 4 System Clocks Cascade DLLs Convert Clock Levels using Select I/O DLL3 DLL4 Generate Clocks multiply divide shift Delay locked loops synchronize on-chip and board level clocks

Power-down Mode Controlled by single power down pin All inputs blocked, appear low internally All outputs disabled All register states preserved Power-down status pin Synchronous wake up 100 uA typical A dedicated Power Down pin helps conserve the power resources.

There are four ways to program a Spartan-II FPGA Configuration Modes The user can choose the configuration mode that best suits the particular application. There are four ways to program a Spartan-II FPGA

Partial Reconfiguration Frame by frame reconfiguration supported while device is running Routing changes affect device operation Re-initializing a block RAM requires stopping all access in that column Can dynamically load the required logic at a given time Minimizes cost further by time-multiplexing the logic resources

Spartan-II Architecture Summary Delivers all the key requirements for ASIC replacement 200,000 gates 200 MHz Flexible I/O interfaces On-chip distributed and block RAM Clock management Low power Complete development system support