C ONTINUOUS A SSIGNMENTS

C OMBINATIONAL L OGIC C IRCUITS each output of a Combinational Logic Circuit  A function of the inputs - Mapping functions (fo, f1, f2, …fm) the outputs are updated immediately after the inputs change  Don’t forget the propagation delay in real circuits

D ATAFLOW M ODELLING only model behaviour of combinational logic circuits assign a value to a net using continuous assignment (CA) statement continuous assignment corresponds to combinational logic, without requiring explicit instantiation of gates flip-flops and latches can NOT be created using continuous assignment continuous assignments are always active source order of the CA statements does not impact the design CA statements are executed concurrently

C ONTINUOUS A SSIGNMENTS MEANING A continuous assignment is the most basic statement in dataflow modeling, used to drive a value onto a net. A continuous assignment replaces gates in the description of the circuit and describes the circuit at a higher level of abstraction. A continuous assignment statement starts with the keyword assign.

A SIMPLE DATAFLOW EXAMPLE Assign c = a&&b; “ assign ” is the keyword carrying out the assignment operation. This types of assignment is called a continuous assignment. a and b are operands – typically single-bit logic variables. “&&” is a logic operator. It does the bit-wise AND operation on the two operands a and b. “=“ is an assignment activity carried out. C is a net representing the signal which is the result of the assignment.

C ONTINUOUS A SSIGNMENTS SYNTAX //Syntax of assign statement in the simplest form ::= assign ? ? ; Example: / / Continuous assign. out is a net. i 1 and i 2 are nets. assign out = i 1 & i 2 ; // Continuous assign for vector nets. addr is a 16-bit vector net // addrl and addr2 are 16-bit vector registers. assign addr[l5:0] = addrl_bits[l5:0] * addr2_bits[l5:0]; // Concatenation. Left-hand side is a concatenation of a scalar // net and a vector net. assign {c_out, sum[3:0]) = a[3:0] + b[3:0] + c_in;

D ATAFLOW EXAMPLE AND-OR-INVERT

8 E XAMPLE : M ULTIPLEXER

9 E XAMPLE Example: Half Adder Compare the two Verilog modules and comment their final implementations. Ans: The ‘+’ operator is not bound directly to physical gates

Example: Full Adder

Example: Given:Tpd(AND) = 10ns Tpd(XOR) = 15ns `timescale 1ns/100ps module Half_Adder (CO, SUM, A, B); output CO, SUM; input A, B; assign #10 CO = A & B; assign #15 SUM = A ^ B; endmodule

E XAMPLE : 4X1 M U X USING LOGIC EQUATIONS // Module 4-to-1 multiplexer using data flow logic equation // Compare to gate-level model module mux4_to_1 (out, i 0, i 1, i 2, i 3, s 1, s 0 ); // Port declarations from the I/O diagram output out; input i 0, i 1, i 2, i 3 ; input s 1, s 0 ; // Logic equation for out assign out = (~s 1 & ~s 0 & i 0 ) | (~s 1 & s 0 & i 1 ) | (s 1 & ~s 0 & i 2 ) |(s 1 & s 0 & i 3 ) ;

4- TO -1 M ULTIPLEXER, U SING C ONDITIONAL O PERATORS / / Module 4-to-1 multiplexer using data flow. Conditional operator. / / Compare to gate-level model module multiplexer4-to-1 (out, i 0, i 1, i 2, i 3, s 1, s 0 ); / / Port declarations from the I/O diagram output out; input i 0, i 1, i 2, i 3 ; input s 1, s 0 ; / / Use nested conditional operator assign out = s 1 ? ( s 0 ? i 3 : i 2 ) : (s 0 ? i l : i 0 ) ; endmodule