Unit 2 Combinational Circuits

Introduction Logic circuits for digital systems may be either combinational or sequential. A combinational circuit consists of logic gates whose outputs present at any time are determinedfromonlythe combinationof inputs.

CombinationalCircuits A combinational circuits 2 possible combinations n ofinputvalues n input variables m output variables Specific functions  Adders, subtractors, multiplexers comparators,decoders,encoders,and  MSI circuitsorstandard cells Combinational Logic Circuit

AnalysisProcedure Step 1: Label all gate outputs that are a function of input variables with arbitrary symbols – but with meaningful names. Determine the Boolean functions for each gate output. Step 2: Label the gates that are a function of input variables and previously labeled gates with other arbitrary symbols. Find the Boolean functions for these gates. Step 3: Repeat the process outlined in step 2 until outputs of the circuit are obtained. the Step 4: By repeated substitution of previously defined functions, obtain the output Boolean functions in terms of input variables.

AnalysisProcedure Example Astraight-forwardprocedure

AnalysisProcedure Example Step 1: F 2 T 1 T 2 Ste p = AB+AC+BC = A+B+C = ABC 2: T 3 = F 2 'T 1 Step 3: F 1 = T 3 +T 2 Step 4: F 1 = T 3 +T 2 = F 2 'T 1 +ABC ======== (AB+AC+BC)'(A+B+C)+ABC (A'+B')(A'+C')(B'+C')(A+B+C)+ABC (A'+B'C')(AB'+AC'+BC'+B'C)+ABC A'BC'+A'B'C+AB'C'+ABC

TruthTable

DesignProcedure The design procedure of combinational circuits Step 1: State the problem (system spec.) Step 2: From the specifications of the circuits, determine the required number of inputs and outputs and assign a symbol to each. Step 3: Derive the truth table that defined the required relationship between inputs and outputs Step 4: Obtain the simplified Boolean functions for each output as a function of the input variables. Step 5: Draw the logic diagram and verify correctness of the design (manually or by the simulation).

DesignMethodand Constraint Functional description Boolean function HDL (Hardware description  Verilog HDL  VHDL Schematic entry Logic constraint number of gates number of inputs to a gate propagation delay number of interconnections language) limitations of the driving capabilities

BCDtoExcess-3Code Conversion

BCDtoExcess-3Code Conversion

BCDtoExcess-3Code Conversion Simplified functions z y x ====== D' CD +C'D' B'C + B'D+BC'D' w = A+BC+BD Efficient implementation z y x w ======== D' CD +C'D'= CD + (C+D)‘ B'C + B'D+BC'D‘ = B'(C+D) +B(C+D)' A+BC+BD=A+B(C+D)

LogicDiagramforBCDto Excess-3 CodeConverter

1-BitHalf Adder Half adder = 0 ; = 1 ; = 1 ; = two input variables: x, y (10) 2 two outputvariables:C(carry), S (sum) truthtable S = x'y+xy'=x  y= C = xy= (x'+y')' S' = xy+x'y' S = (C+x'y')' (x+y)(x'+y')

LogicDiagramof1-Bit Half Adder

Lan-Da Van DCD- 1-BitFullAdder Full-Adder The arithmetic sum of three input bits three input bits  x, y: two significant bits  z: the carry bit from the previous lower significant bit Twooutputbits:C,S Sum Carry

LogicDiagramof1-Bit Full Adder

LogicDiagramof1-Bit Full Adder S = x'y'z+x'yz'+ xy'z'+xyz = x’(y  z) +x(y  z)’ = x  y  z C = xy + xz + yz = xy + xyz + xy’z + xyz + x’yz = xy + z (x  y + xy) = xy + z (x  y)

4-BitFullAdder Binaryadder

Subtractors Half Subtractor Full Subtractor Adder/Subtractor - 1 Adder/Subtractor - 2

Half Subtractor CABD A 0 B 0 D 0 C

Full Subtractor C i A i B i D i C i CiCi AiBiAiBi DiDi D i = C i $ (A i $ B i ) Same as S i in full adder

Full Subtractor C i A i B i D i C i+1 CiCi AiBiAiBi C i+1 C i+1 = !A i & B i # C i & !A i & !B i # C i & A i & B i

Full Subtractor C i+1 = !A i & B i # C i & !A i & !B i # C i & A i & B i C i+1 = !A i & B i # C i & (!A i & !B i # A i & B i ) C i+1 = !A i & B i # C i & !(A i $ B i ) Recall: D i = C i $ (A i $ B i ) C i+1 = !A i & B i # C i & !(A i $ B i )

Full Subtractor D i = C i $ (A i $ B i ) C i+1 = !A i & B i # C i & !(A i $ B i ) half subtractor

CarryLookaheadAdder (1/7) Given Stage i from a Full Adder, we know that there will be a carry generated when A i = B i = "1", whether or not there is a carry-in. AiAi BiBi GiGi Alternately, there propagated if the and a carry-in, C i These two signal will be a carry “ half-sum ” is "1" occurs. i conditionsare G i, and CiCi called generate, denoted as propagate, denoted as P i respectively and are identified in the circuit. C i+1 SiSi P

CarryLookaheadAdder (2/7) In the ripple carry adder: G i, P i, and S i are local function to each cell of the adder C i is also local function for each cell In the carry lookahead adder, in order to reduce the length of the carry chain, C i is changed to a more global function spanning multiple cells Defining the equations the P i and G i : forthe Full Adder in term of   PiSiPiSi AiAi BiBi G i C i  1 A i B i   P i  C i G i P i C i

CarryLookaheadAdder (3/7) C i+1 can be removed from the cells and used to derive a set of carry equations spanning multiple Beginning at the cell 0 with carry in C 0 : cells. C1C2C1C2 ============ G0G1G1G2G2G3G0G1G1G2G2G P 0 C 0 P 1 C 1 = G 1 + P 1 (G 0 + P 0 C 0 ) P 1 G 0 + P 1 P 0 C 0 C3C3 P 2 C 2 =G 2 + P 2 (G 1 + P 1 G 0 +P 1 P 0 C 0 ) P 2 G 1 + P 2 P 1 G 0 + P 2 P 1 P 0 C 0 C4C4 P 3 C 3 = G 3 + P 3 G 2 + P 3 P 2 G P 3 P 2 P 1 P 0 C 0 P3P2P1G0P3P2P1G0

CarryLookaheadAdder (4/7)

CarryLookaheadAdder (5/7)

CarryLookaheadAdder (6/7) CLA GEN

CarryLookahead Adder(7/7) This lookahead scheme could be extended to more than four bits; in practice, due to limited gate fan-in, such extension is not feasible. Instead, the concept is extended another level by considering group generate (G 0-3 ) and group propagate (P 0-3 ) functions:  G 0  3 G 3 P 3 G 2 P 3 P 2 G 1 P 3 P 2 P 1 G 0 Using these twoequations:  C 4 = G 3 + P 3 C 3 = G 3 + P 3 G 2 + P 3 P 2 G 1 + P 3 P 2 P 1 G 0 + P 3 P 2 P 1 P 0 C 0 P03P03 P 3 P 2 P 1 P 0  C 4 G 0  3 P03P03 C 0 Thus, it is generator possible circuit to to have five 4-bit carry lookahead speed up 16-bit addition (see next slide).

16-bit2-levelCarry Lookahead Adder c9c9 c3c3 c 11 c8c8 c4c4 G 14 P 14 G 10 P 10 GP G 13 P 13 G 15 P 15 c 12 c4c4 c0c0 c8c8 G P G 4-7 G 0-3 G 8-11 P 4-7 P 0-3 P 8-11 G 0-15 P 0-15 CLA GEN G3P3G3P3 G2P2G2P2 G1P1G1P1 G0P0G0P0 G7P7G7P7 G6P6G6P6 G5P5G5P5 G4P4G4P4 11 G9P9G9P9 G8P8G8P8 CLA GEN G 12 P 12 CLA GEN

4-BitAdder/Subtractor A-B = A+(2’s complement 4-bit adder-subtractor ofB) M=0,A+B;M=1,A+B’+1

Overflow Discussion Overflow The storage is limited. Add two positive numbers and obtain a negative number Add two negative numbers and obtainapositive V = 0,nooverflow;V=1,overflow Example:

BCDAdder Add two decimal digits in BCD together with an a previous stage 9 inputs: two BCD's and one carry-in 5 outputs: one BCD and one carry-out Design approaches input carry from Since each input digit does not exceed 9, the output sum grater than =19, where 1 denotes an input carry. A truth table with 19 entries Use two 4-bit binary full adders cannotbe Modifications are needed C = 1  K = 1 if thebinarysum>9  Z 8 Z 4 = 1  Z 8 Z 2 = 1 modification: C = K +Z Z + Z Z

TruthTableofBCDAdder

LogicDiagramofBCD Adder BCD BCD Output

BinaryMultiplier

4-Bitby3-BitBinaryMultiplier

MagnitudeComparator The comparison of two numbers outputs: A>B, A=B, A<B Design Approaches the truth table  2 entries - too cumbersome for large n use inherent regularity of the problem  reduce design efforts  reduce human errors Algorithm -> logic A = A 3 A 2 A 1 A 0 ; B = B 3 B 2 B 1 B 0 A=B if A 3 =B 3, A 2 =B 2, A 1 =B 1 and A 0 =B 0  equality: x i = A i B i +A i 'B i '  (A=B) = x 3 x 2 x 1 x 0 (A>B) = A 3 B 3 '+x 3 A 2 B 2 '+x 3 x 2 A 1 B 1 '+x 3 x 2 x 1 A 0 B 0 ' (A<B) = A 3 'B 3 +x 3 A 2 'B 2 +x 3 x 2 A 1 'B 1 +x 3 x 2 x 1 A 0 'B 0 Implementation x i = (A i B i '+A i 'B i )' 2n

Four-BitMagnitude Comparator

Decoder An n-to-m decoder n a binary code of n bits = 2 distinct information n input variables; up to 2 output lines n onlyoneoutputcanbeactive(high)atanytime

Three-to-EightLine Decoder x’y’z’

DecoderwithEnable /Demultiplexer Demultiplexers a decoder with an enable input receive information on asinglelineandtransmitsitononeof n 2 possibleoutputlines 0 Two-to-four-line decoderwith enable input

DecoderwithEnable /Demultiplexer

4x16Decoder Expansion two3-to-8decoder:a4-to-16decoder 4  16 decoder constructed with 3  8 decoders two

CombinationalLogic Implementation Each output = a minterm Use a decoder and an external OR gate toimplementany Boolean function of A full-adder S(x,y,x)=  (1,2,4,7) C(x,y,z)=  (3,5,6,7) ninput variables

Lan Encoder with threeOR gates. The encoder can be implemented z  D 1  D 3  D 5  D 7 y  D 2  D 3  D 6  D 7 x  D 4  D 5  D 6  D 7

Encoder Animplementation x=D 4 +D 5 +D 6 +D 7 y=D 2 +D 3 +D 6 +D 7 z=D 1 +D 3 +D 5 +D 7 limitations  illegal input: e.g. D 3 =D 6 =1  the output = 111 (¹3 and ¹6)

Priority Encoder Resolve the ambiguity of illegal inputs Only oneoftheinput is encoded LSBMSB D 3 has the highest priority the lowest priority D 0 has X: don't-care conditions V: valid output indicator

PriorityEncoder 1

PriorityEncoder x  D 2  D 3 y  D 3  D 1 D 2 V  D 0  D 1  D 2  D 3

Multiplexer Select binary information from one of many input lines and direct it to a single output line n 2 input lines, n selection linesandoneoutputline E.g.:2-to-1-linemultiplexer Two-to-one-linemultiplexer

4-to-1-LineMultiplexer

BooleanFunction Implementation Using MUX MUX: a decoder + an OR gate 2 -to-1 MUX can implement any Boolean function of n input variable. Procedure: assign an ordering sequence of the input variable the rightmost variable (D) will be used for the input lines assign the remaining n-1 variables to the selection lines w.r.t. their corresponding sequence construct the truth table n consider a pair of consecutive determine the input lines minterms starting from m 0

BooleanFunction Implementation Using MUX Example:GivenF(x,y,z) =  (1,2,6,7)

BooleanFunction Implementation Using MUX Example:GivenF(A,B,C,D) =  (1, 3, 4,11,12,13,14,15)

Three-StateGate A multiplexer gates. can be constructed with three-state Outputstate:0,1,andhigh-impedance(openckts)

Four-to-One-LineMultiplexer

Conclusion Adder/Subtractor Multiplier Decoder Encoder Multiplexer