Chapter 5: Computer Systems Organization Invitation to Computer Science, C++ Version, Third Edition

Invitation to Computer Science, C++ Version, Third Edition 2 Objectives In this chapter, you will learn about: The components of a computer system Putting all the pieces together – the Von Neumann architecture The future: non-Von Neumann architectures

Invitation to Computer Science, C++ Version, Third Edition 3 Introduction Computer organization examines the computer as a collection of interacting “functional units” Functional units may be built out of the circuits already studied Higher level of abstraction assists in understanding by reducing complexity

Invitation to Computer Science, C++ Version, Third Edition 4 Figure 5.1 The Concept of Abstraction

Invitation to Computer Science, C++ Version, Third Edition 5 The Components of a Computer System Four functional units:  Memory  Input/Output  Arithmetic/Logic unit  Control unit Sequential execution of instructions Stored program concept Von Neuman Architecture

Invitation to Computer Science, C++ Version, Third Edition 6 Figure 5.2 Components of the Von Neumann Architecture

Invitation to Computer Science, C++ Version, Third Edition 7 Memory and Cache Information stored and fetched from memory subsystem Random Access Memory associates addresses with physical memory locations Cache memory keeps values currently in use in faster memory to speed access times

Invitation to Computer Science, C++ Version, Third Edition 8 Memory and Cache (continued) RAM (Random Access Memory )  Memory made of addressable “cells”  Current standard cell size is 8 bits  All memory cells accessed in equal time  Memory address Unsigned binary number N long Address space is then 2 N cells

Invitation to Computer Science, C++ Version, Third Edition 9 Figure 5.3 Structure of Random Access Memory

Invitation to Computer Science, C++ Version, Third Edition 10 Memory and Cache (continued) Parts of the memory subsystem  Fetch/store controller Fetch: retrieve a value from memory Store: store a value into memory  Memory address register (MAR)  Memory data register (MDR)  Memory cells, with decoder(s) to select individual cells

Invitation to Computer Science, C++ Version, Third Edition 11 Memory and Cache (continued) Fetch operation  The address of the desired memory cell is moved into the MAR  Fetch/store controller signals a “fetch,” accessing the memory cell  The value at the MAR’s location flows into the MDR

Invitation to Computer Science, C++ Version, Third Edition 12 Memory and Cache (continued) Store operation  The address of the cell where the value should go is placed in the MAR  The new value is placed in the MDR  Fetch/store controller signals a “store,” copying the MDR’s value into the desired cell

Invitation to Computer Science, C++ Version, Third Edition 13 Memory and Cache (continued) Memory register  Very fast memory location  Given a name, not an address  Serves some special purpose  Modern computers have dozens or hundreds of registers

Invitation to Computer Science, C++ Version, Third Edition 14 Figure 5.7 Overall RAM Organization

Invitation to Computer Science, C++ Version, Third Edition 15 Cache Memory Memory access is much slower than processing time Faster memory is too expensive to use for all memory cells Locality principle  Once a value is used, it is likely to be used again Small size, fast memory just for values currently in use speeds computing time

Invitation to Computer Science, C++ Version, Third Edition 16 Memory Types Link to Discussion of Memory

Invitation to Computer Science, C++ Version, Third Edition 17 Input/Output and Mass Storage Communication with outside world and external data storage  Human interfaces: monitor, keyboard, mouse  Archival storage: not dependent on constant power External devices vary tremendously from each other

Invitation to Computer Science, C++ Version, Third Edition 18 Input/Output and Mass Storage (continued) Volatile storage  Information disappears when the power is turned off  Example: RAM Nonvolatile storage  Information does not disappear when the power is turned off  Example: mass storage devices such as disks and tapes

Invitation to Computer Science, C++ Version, Third Edition 19 Input/Output and Mass Storage (continued) Mass storage devices  Direct access storage device Hard drive, CD-ROM, DVD, etc. Uses its own addressing scheme to access data  Sequential access storage device Tape drive, etc. Stores data sequentially Used for backup storage these days

Invitation to Computer Science, C++ Version, Third Edition 20 Input/Output and Mass Storage (continued) Direct access storage devices  Data stored on a spinning disk  Disk divided into concentric rings (tracks)  Read/write head moves from one ring to another while disk spins  Access time depends on: Time to move head to correct track Time for sector to spin to data location

Invitation to Computer Science, C++ Version, Third Edition 21 Disk Data Layout ( from Stallings COA 7e )

Invitation to Computer Science, C++ Version, Third Edition 22 Components of a disk drive - platter - surface -read/write head Fig from Stallings,COA 7e

Invitation to Computer Science, C++ Version, Third Edition 23 Tracks and Cylinders - Gray portion represents a cylinder

Invitation to Computer Science, C++ Version, Third Edition 24 Figure 5.8 Overall Organization of a Typical Disk

Invitation to Computer Science, C++ Version, Third Edition 25 Sample Disk Parameters Number of tracks / surface 1,000 Number of sectors / track 64 Number of bytes / sector 1,024 Rotation Speed 7200 rev / min 120 rev / sec 8.33 msec /rev Arm Movement Time 0.02 msec / track

Invitation to Computer Science, C++ Version, Third Edition 26 Sample Disk Calculations Disk Storage Capacity Surfaces x tracks/surface x sector/track x bytes/sector 1 x 1,000 x 64 x 1,024 = 65,535,000 ( 64 Megabytes ) Disc Access Time Seek Time – r/w head movement time to proper track Latency – wait for sector to rotate under r/w head Transfer time – time for sector to rotate under head

Invitation to Computer Science, C++ Version, Third Edition 27 Access time varies depending on Where the r/w head is located Where the requested sector is located Seek TimeBest Case = 0 msec ( no arm movement needed) Worst Case = 999 x 0.02 = msec (move from track 0 to track 999 Average Case = 300 x 0.02 = 6 msec ( assume avg move of 300 tracks ) LatencyBest Case = 0 msec ( sector is just about to pass under the r/w head ) Worst case = 8.33 msec ( we have just missed the sector wait a complete rev ) Average Case = 4.17 msec ( one-half a revolution ) Transfer1/64 x 8.33 msec = 0.13 msec ( time for one sector to pass under the r/w head) Best = 0.13 msec Worst = msec Average = 10.3 msec

Invitation to Computer Science, C++ Version, Third Edition 28 From Stallings, COA 7e

Invitation to Computer Science, C++ Version, Third Edition 29 Hard Disk Mean Time To Failure The MTTF value published in manufacturer literature is often misunderstood. ( sometimes Mean Time Between Failure ) In this example the MTTF is listed as 300,000 hours. This does not mean that the hard drive will last for years. Hard drives may have on average a serviceable lifetime of 5 years or so. The manufacturer tests a lot of hard drives continuously during their serviceable lifetime. In this case, on average, 1 failure occurs every 300,000 drive-hours of testing.

Invitation to Computer Science, C++ Version, Third Edition 30 Input/Output and Mass Storage (continued) I/O controller  Intermediary between central processor and I/O devices – speed difference (10 ns vs 10 msec)  Processor sends request and data, then goes on with its work  I/O controller interrupts processor when request is complete

Invitation to Computer Science, C++ Version, Third Edition 31 Figure 5.9 Organization of an I/O Controller

Invitation to Computer Science, C++ Version, Third Edition 32 The Arithmetic/Logic Unit Actual computations are performed Primitive operation circuits  Arithmetic (ADD, etc.)  Comparison (CE, etc.)  Logic (AND, etc.) Data inputs and results stored in registers Multiplexor selects desired output

Invitation to Computer Science, C++ Version, Third Edition 33 The Arithmetic/Logic Unit (continued) ALU process  Values for operations copied into ALU’s input register locations  All circuits compute results for those inputs  Multiplexor selects the one desired result from all values  Result value copied to desired result register

Invitation to Computer Science, C++ Version, Third Edition 34 Three register ALU organization

Invitation to Computer Science, C++ Version, Third Edition 35 Multi-Register ALU Orgainization

Invitation to Computer Science, C++ Version, Third Edition 36 Figure 5.12 Using a Multiplexor Circuit to Select the Proper ALU Result

Invitation to Computer Science, C++ Version, Third Edition 37 Overall ALU Organization

Invitation to Computer Science, C++ Version, Third Edition 38 The Control Unit Manages stored program execution Task  Fetch from memory the next instruction to be executed  Decode it: determine what is to be done  Execute it: issue appropriate command to ALU, memory, and I/O controllers

Invitation to Computer Science, C++ Version, Third Edition 39 Machine Language Instructions Can be decoded and executed by control unit Parts of instructions  Operation code (op code) Unique unsigned-integer code assigned to each machine language operation  Address field(s) Memory addresses of the values on which operation will work

Invitation to Computer Science, C++ Version, Third Edition 40 Figure 5.14 Typical Machine Language Instruction Format

Invitation to Computer Science, C++ Version, Third Edition 41 Machine Language Instructions… Operations of machine language  Data transfer (Move values to and from memory and registers) Memory cell → ALU register ALU register → memory cell One memory cell → another memory cell One ALU register → another ALU register

Invitation to Computer Science, C++ Version, Third Edition 42 Machine Language Instructions… Operation Type Meaning ( examples are based on simulated machine used in labs 8-10) LOAD XLoad register R with the contents of memory cell X CON(X)  R Example: STORE XStore the contents of register R into memory cell X R  CON(X) Example: * MOVE X,YCopy the contents of memory cell X into memory cell Y * operation type n.a. on simulated lab machine

Invitation to Computer Science, C++ Version, Third Edition 43 Machine Language Instructions (continued) Operations of machine language  Arithmetic/logic Perform ALU operations that produce numeric values ArithOp X,Y,Z ArithOp X, Y ArithOp X where ArithOP  {ADD, SUB, MULT, DIV 

Invitation to Computer Science, C++ Version, Third Edition 44 Machine Language Instructions… Operation Type Meaning ( examples are based on simulated machine used in labs 8-10) * ADD X, Y, Z 3-address instruction Add the contents of memory cell X to the contents of memory cell Y, and put the result into memory cell Z. CON(Z) = CON(X) + CON(Y) * ADD X, Y 2-address instruction Add the contents of memory cell X to the contents of memory cell Y, and put the result into memory cell Y. CON(Y) = CON(X) + CON(Y) ADD X 1-address instruction Add the contents of memory cell X to the contents of register R. Put the result into register R. R = CON(X) + R Example: * operation type n.a. on simulated lab machine

Invitation to Computer Science, C++ Version, Third Edition 45 Machine Language Instructions… Operations of machine language (continued)  Compares Set bits of status register or condition register to hold result of a comparison Assume there is a 3-bit condition register. GTEQLT 100 A ‘1’ indicates that the given condition holds, Greater Than, EQual To or Less Than

Invitation to Computer Science, C++ Version, Third Edition 46 Machine Language Instructions… Operation Type Meaning ( examples are based on simulated machine used in labs 8-10) * COMPARE X,Y Compare the contents of memory cell X to the contents of memory cell Y and set the condition codes accordingly CON(X) > CON(Y) => GT =1, EQ =0, LT =0 CON(X) = CON(Y) => GT =0, EQ =1, LT =0 CON(X) GT =0, EQ =0, LT =1 COMPARE XCompare the contents of memory cell X to the contents of the R register and set condition codes accordingly CON(X) > CON(R) => GT =1, EQ =0, LT =0 CON(X) = CON(R) => GT =0, EQ =1, LT =0 CON(X) GT =0, EQ =0, LT =1 Example: * operation type n.a. on simulated lab machine

Invitation to Computer Science, C++ Version, Third Edition 47 Machine Language Instructions… Operations of machine language (continued)  Branches Normally, operation is sequential Branch instructions alter the normal sequential flow of program execution Usually the decision to branch is based on condition codes

Invitation to Computer Science, C++ Version, Third Edition 48 Machine Language Instructions… OperationMeaning ( examples are based on simulated machine used in labs 8-10) JUMP X Take the next instruction unconditionally from memory cell X Example: JUMPGT X If the GT indicator (bit, flag) is a 1, PC  X Example : JUMPEQ and JUMPLT work in a similar fashion. * JUMPGE X If either the GT or the EQ indicator (bit, flag) is a 1, PC  X JUMPLE and JUMPNEQ work in a similar fashion. HALT Stop program execution. Don’t go to the next step * operation type n.a. on simulated lab machine

Invitation to Computer Science, C++ Version, Third Edition 49

Invitation to Computer Science, C++ Version, Third Edition 50 Machine Language Practice PseudocodeAddrContentsComment 100Value of a 101Value of b 102Value of c 103Value of d Set a to the value b + c + d 50LOAD 101Put value of b into R 51ADD 102Add value of c to R 52ADD 103Add value of d to R 53STORE 100Store value in R to a 54HALTStop processing Set a to the value b + c + d

Invitation to Computer Science, C++ Version, Third Edition 51 Machine Language Practice AddressContentsComment (0) Put value of b into R (load 9) (1) ( a vs b) ? (compare 8) (2) IF (EQ = 0) then PC  5 (bne 5) (3) Load value of c into R (load 10) (4) Store value in R to d (store 11) (5) Halt (8) Value of a = (9) Value of b = (10) Value of c = (11) Value of d = 8 (initially) If (a = b) then set d to the value of c

Invitation to Computer Science, C++ Version, Third Edition 52 PseudocodeAddrContentsComment 100Value of a 101Value of b 102Value of c 103Value of d Initialize a to the value d50LOAD 103CON(d) → R 51STORE 100CON(R) → a While a  c set value of a to the value ( a+ b) Endwhile 52LOAD 102CON(c) → R 53COMPARE 100 a ? c 54JUMPGT 59 If (GT = 1) PC  59 55LOAD 100 a  a + b 56ADD STORE JUMP 52Go to top of loop 59….Instruction after While stmt

Invitation to Computer Science, C++ Version, Third Edition 53 Control Unit Registers And Circuits Parts of control unit  Links to other subsystems  Instruction decoder circuit  Two special registers: Program Counter (PC)  Stores the memory address of the next instruction to be executed Instruction Register (IR)  Stores the code for the current instruction

Invitation to Computer Science, C++ Version, Third Edition 54 Figure 5.16 Organization of the Control Unit Registers and Circuits

Invitation to Computer Science, C++ Version, Third Edition 55 Putting All the Pieces Together—the Von Neumann Architecture Subsystems connected by a bus  Bus: wires that permit data transfer among them At this level, ignore the details of circuits that perform these tasks: Abstraction! Computer repeats fetch-decode-execute cycle indefinitely

Invitation to Computer Science, C++ Version, Third Edition 56 Figure 5.18 The Organization of a Von Neumann Computer

Invitation to Computer Science, C++ Version, Third Edition 57 Binary OpcodeOperationMeaning 0000LOAD X CON(X)  R 0001STORE X R  CON(X) 0010CLEAR X 0  CON(X) 0011ADD X R + CON(X)  R 0100INCREMENT X CON(X) + 1  CON(X) 0101SUBTRACT X R - CON(X)  R 0110DECREMENT X CON(X) - 1  CON(X) 0111COMPARE X if CON(X) > R then set GT to 1, else 0 if CON(X) = R then set EQ to 1, else 0 if CON(X) < R then set LT to 1, else JUMP XJump to location X 1001JUMPGT XJump to location X if GT = JUMPEQ XJump to location X if EQ = JUMPLT XJump to location X if LT = JUMPNEQ XJump to location X if EQ = IN XInput an integer into location X 1110OUT XOutput an integer from location X 1111HALTStop program execution

Invitation to Computer Science, C++ Version, Third Edition 58 The Future: Non-Von Neumann Architectures Physical limitations on speed of Von Neumann computers Non-Von Neumann architectures explored to bypass these limitations Parallel computing architectures can provide improvements: multiple operations occur at the same time

Invitation to Computer Science, C++ Version, Third Edition 59 The Future: Non-Von Neumann Architectures (continued) SIMD architecture  Single instruction/Multiple data  Multiple processors running in parallel  All processors execute same operation at one time  Each processor operates on its own data  Suitable for “vector” operations

Invitation to Computer Science, C++ Version, Third Edition 60 Figure 5.21 A SIMD Parallel Processing System

Invitation to Computer Science, C++ Version, Third Edition 61 MIMD architecture  Multiple instruction/Multiple data  Multiple processors running in parallel  Each processor performs its own operations on its own data  Processors communicate with each other The Future: Non-Von Neumann Architectures (continued)

Invitation to Computer Science, C++ Version, Third Edition 62 Figure 5.22 Model of MIMD Parallel Processing

Invitation to Computer Science, C++ Version, Third Edition 63 Summary of Level 2 Focus on how to design and build computer systems Chapter 4  Binary codes  Transistors  Gates  Circuits

Invitation to Computer Science, C++ Version, Third Edition 64 Summary of Level 2 (continued) Chapter 5  Von Neumann architecture  Shortcomings of the sequential model of computing  Parallel computers

Invitation to Computer Science, C++ Version, Third Edition 65 Summary Computer organization examines different subsystems of a computer: memory, input/output, arithmetic/logic unit, and control unit Machine language gives codes for each primitive instruction the computer can perform, and its arguments Von Neumann machine: sequential execution of stored program Parallel computers improve speed by doing multiple tasks at one time