Large-Scale SRAM Variability Characterization Chip in 45nm CMOS  High end microprocessors continue to require larger on-die cache memory  > 6σ of statistics needed to capture the variability of large cache memories  Problem: Getting statistics across large designs is $$ and difficult  Solution: Customized instrumentation on-chip

Large-Scale SRAM Variability Characterization Chip in 45nm CMOS Conventional Metrics – RSNM, I W, etc.  Limited silicon data  Cannot correlate to cell bit fails in functional SRAM SRAM macros  All-internal-node access  360 CUTs per chip 2.2mm×2.2mm

Large-Scale SRAM Variability Characterization Chip in 45nm CMOS Large-Scale SRAM Metrics – SRRV, WWTV, etc.  Silicon data measured for each SRAM cell  Characterized under natural operating environment  Correlate to cell bit fails in functional SRAM Functional SRAM arrays  Direct bit-line access  768Kb per chip 2.2mm×2.2mm

Large-Scale SRAM Variability Characterization Chip in 45nm CMOS  The large-scale read/write margin measurements showed excellent correlation, near failure, to SRAM DC RSNM and I W measurements  µ/σ yield estimates has been shown to be highly dependent on the read stability or writeability metric used and is therefore unsuitable for estimating yield  Large-scale characterization of SRAM read stability and writeability is critical for SRAM failure modeling and can be used to complement BIST and nano-probing  Acknowledgement: NSF, C2S2, IBM Faculty Partnership Award, STMicroelectronics