1 Very Large Scale Integration II - VLSI II Memory Structures Hayri Uğur UYANIK Devrim Yılmaz AKSIN ITU VLSI Laboratories Istanbul Technical University

2 Outline History Lesson General Memory Structure Memory Cell Types – Volatile SRAM DRAM – Non-Volatile MPROM EPROM OTP & UV-EPROM E 2 PROM FeRAM Memristor Sense Amplifiers – Voltage Sense Amplifiers – Current Sense Amplifiers Address Decoder Memory Modelling In Verilog References

3 History Lesson Delay line memory – Piezoelectric pulses within mercury – One of the earliest electronic (?) memory – 1000 word storage

4 General Memory Structure

5 Memory Cell Types Volatile – SRAM – DRAM Non-Volatile – MPROM – EPROM OTP UV-EPROM E 2 PROM – FeRAM – Memristor

6 SRAM Static Random Access Memory

7 SRAM Not area efficient  No special semiconductor process Fast Low power consumption Easy to communicate Used in – Embedded systems – CPU Cache – FPGA CPLD LUT

8 DRAM Dynamic Random Access Memory

9 DRAM Area efficient Very area efficient Needs special semiconductor process  Slow  Hard to communicate with  High power consumption  Needs refreshing  Used in – Computer primary storage – Video card primary storage – Cell Phones, PDAs

10 DRAM Types Asynchronous DRAM Synchronous DRAM (SDRAM) – Single Data Rate (SDR SDRAM) – Dual Data Rate (DDR SDRAM) Both rising and falling edge Memory cells are slow compared to bandwidth demand Bandwidth is increased by increasing the I/O buffer data rate (DDR2 and DDR3) – Dual DDR Communicate with two different RAM slots at the same time

11 DRAM Types

12 Dual Ported RAM SRAMs and DRAMs can be dual ported – can read from and write to two different addresses at the same time – Mostly effective in Video processing – One port filling the RAM, one port is reading for display CPU registers FIFOs

13 MPROM Mask Programmable ROM

14 MPROM Programmed at the fab  – Route metal interconnects – Increase V T Change channel implant Change gate oxide thickness One time programmable  Only few masks are changed Cheap in large volume Used in – Old video games – Sound data in electronic music instruments – Electronic dictionaries

15 OTP & UV-EPROM One Time Programmable ROM UV Erasable Programmable ROM

16 OTP & UV-EPROM 1. High V G and V D creates hot electrons 2. They penetrate gate oxide 3. They become trapped in the floating polysilicon 4. Additional negative charge below the gate increases V T (For a 5V ROM, V T increases from 1V to 8V)

17 OTP & UV-EPROM OTP and UV-EPROM are the same – OTP has a opaque plastic package (cheaper) – UV-EPROM has a package with transparent quartz window (expensive)  Need special semiconductor process  Slow write  High power consumption when writing  Fast read OTP data is permanent  UV-EPROMs can be erased – When exposed to UV light for 20 minutes 

18 E 2 PROM Electrically Erasable Programmable ROM

19 E 2 PROM Erasing: – V D =0, V S =0, V G =High (e.g. 15V) – Floating gate becomes positively charged Fowler-Nordheim Tunneling – V T below floating gate (V TFG ) drops Making Open Circuit: – EPROM like operation – V D =0, V S =High (e.g. 12V) V G =V TCG – Channel present under control gate – Hot electrons penetrate gate oxide – V TFG increases

20 E 2 PROM Fast read/write Need special semiconductor process  Low power consumption when writing

21 FeRAM Ferroelectric RAM

22 FeRAM Fast read/write Need special semiconductor process  Low power consumption Destructive reading 

Memristor Missing circuit element for 37 years – Concept: Leon Chua – First Realization: HP Labs Final addition to RLC team

Memristor Charge dependent resistance (memristance) Applied voltage or current changes charge (thus the resistance) – Resistance is stored in a non-volatile manner – Can be used to store digital data – Must be read with an AC signal for non-destructive reading (AC does not change stored charge)

Memristor Best of both worlds – Non-volatile – Fast (~f DRAM /10) – Dense (~1Pb/cm 3 ) Has a potential to alter the computer programming paradigm – No need for two sets of memories (fast & volatile for computing, slow & non-volatile for data storage)

26 Sense Amplifiers Voltage Sense Amplifiers

27 Sense Amplifiers Current Sense Amplifiers

28 Address Decoder module ADD_3_8 (in, out); input [2:0] in; output [7:0] out; reg [7:0] out; begin case (in) 3'b000 : out = 8'b ; 3'b001 : out = 8'b ; 3'b010 : out = 8'b ; 3'b011 : out = 8'b ; 3'b100 : out = 8'b ; 3'b101 : out = 8'b ; 3'b110 : out = 8'b ; 3'b111 : out = 8'b ; endcase end endmodule

29 Memory Modelling In Verilog parameter RAM_WIDTH = ; parameter RAM_ADDR_BITS = ; reg [RAM_WIDTH-1:0] [(2**RAM_ADDR_BITS)-1:0]; reg [RAM_WIDTH-1:0] ; [RAM_ADDR_BITS-1:0] ; [RAM_WIDTH-1:0] ; initial $readmemh(" ",,, ); ) begin if ( ) [ ] ; else [ ]; end

30 References fig3.jpg Memory-101-SDR-vs-DDR1-vs-DDR2-vs-DDR3 Memory-101-SDR-vs-DDR1-vs-DDR2-vs-DDR memristor memristor Xilinx Documentation