Circuit design with a commercial 0.13  m CMOS technology for high energy physics applications K. Hänsler, S. Bonacini, P. Moreira CERN, EP/MIC.

Slides:



Advertisements
Similar presentations
Comenius-Minorities in Europe Mobility 4-France.
Advertisements

Barcelona Forum on Ph.D. Research in Communications, Electronics and Signal Processing 21st October 2010 Soft Errors Hardening Techniques in Nanometer.
SAAB SPACE 1 The M2 ASIC A mixed analogue/digital ASIC for acquisition and control in data handling systems Olle Martinsson AMICSA, October 2-3, 2006.
Introduction to CMOS VLSI Design Lecture 18: Design for Low Power David Harris Harvey Mudd College Spring 2004.
Lecture 11: MOS Transistor
1 A Single-supply True Voltage Level Shifter Rajesh Garg Gagandeep Mallarapu Sunil P. Khatri Department of Electrical and Computer Engineering, Texas A&M.
Outline Introduction – “Is there a limit?”
S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 13: Power Dissipation Prof. Sherief Reda Division of Engineering, Brown.
Lecture 5 – Power Prof. Luke Theogarajan
Digital Integrated Circuits© Prentice Hall 1995 Arithmetic Arithmetic Building Blocks.
Lecture 7: Power.
5 th LHC Radiation Day Radiation response of RADMON sensors T. Wijnands (TS/LEA), C. Pignard (TS/LEA) Acknowledgements : UCL Louvain-La-Neuve, PSI Villingen,
LECC 2006 Ewald Effinger AB-BI-BL The LHC beam loss monitoring system’s data acquisition card Ewald Effinger AB-BI-BL.
ACES Workshop 3-4 March, 2009 W. Dabrowski Serial power circuitry in the ABC-Next and FE-I4 chips W. Dabrowski Faculty of Physics and Applied Computer.
Evaluation of 65nm technology for front-end electronics in HEP Pierpaolo Valerio 1 Pierpaolo Valerio -
An Ultra-Low-Power Temperature Compensated Voltage Reference Generator Giuseppe De Vita, Giuseppe Iannaccone Custom Integrated Circuits Conference, 2005.
Dept. of Communications and Tokyo Institute of Technology
Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style Sumeer Goel, Ashok Kumar, and Magdy A. Bayoumi.
Slide: 1International Conference on Electronics, Circuits, and Systems 2010 Department of Electrical and Computer Engineering University of New Mexico.
Mehdi Sadi, Italo Armenti Design of a Near Threshold Low Power DLL for Multiphase Clock Generation and Frequency Multiplication.
Development process of RHBD cell libraries for advanced SOCs
A 30-GS/sec Track and Hold Amplifier in 0.13-µm CMOS Technology
Pierpaolo Valerio.  CLICpix is a hybrid pixel detector to be used as the CLIC vertex detector  Main features: ◦ small pixel pitch (25 μm), ◦ Simultaneous.
1 Radiation tolerance of commercial 130nm CMOS technologies for High Energy Physics Experiments Federico Faccio for the CERN(PH/MIC)-DACEL * collaboration.
Total Ionizing Dose Effects in 130-nm Commercial CMOS Technologies for HEP experiments L. Gonella, M. Silvestri, S. Gerardin on behalf of the DACEL – CERN.
2. Super KEKB Meeting, DEPFET Electronics DEPFET Readout and Control Electronics Ivan Peric, Peter Fischer, Christian Kreidl Heidelberg University.
Filip Tavernier Karolina Poltorak Sandro Bonacini Paulo Moreira
Design of a 10 Bit TSMC 0.25μm CMOS Digital to Analog Converter Proceedings of the Sixth International Symposium on Quality Electronic Design IEEE, 2005.
Process Monitor/TID Characterization Valencia M. Joyner.
SEE effects in deep submicron technologies F.Faccio, S.Bonacini CERN-PH/ESE SEE TWEPP2010.
Development of DC-DC converter ASICs S.Michelis 1,3, B.Allongue 1, G.Blanchot 1, F.Faccio 1, C.Fuentes 1,2, S.Orlandi 1, S.Saggini 4 1 CERN – PH-ESE 2.
Low Power – High Speed MCML Circuits (II)
IEEE Transactions on Circuits and Systems II: Express Briefs
A.Marchioro - CERN/PH1 Accessing 130 nm CMOS Tech for ILC (Public Version) Oct 2006, Munich A. Marchioro CERN, Div. PH 1211 Geneva 23, Switzerland.
Radiation Hardness Test Chip Matthias Harter, Peter Fischer Uni Mannheim.
Fully depleted MAPS: Pegasus and MIMOSA 33 Maciej Kachel, Wojciech Duliński PICSEL group, IPHC Strasbourg 1 For low energy X-ray applications.
Work Package 3 On-detector Power Management Schemes ESR Michal Bochenek ACEOLE Twelve Month Meeting 1st October 2009 WPL Jan Kaplon.
Specifications & motivation 2  Lowering integration time would significantly reduce background  Lowering power would significantly reduce material budget.
ASIC R&D at Fermilab R. Yarema October 30, Long Range Planning Committee2 ASICs are Critical to Most Detector Systems SVX4 – CDF & DO VLPC readout.
Experiment Electronics UMC 0.18µm radiation hardness studies - Update - Sven Löchner 13 th CBM Collaboration Meeting GSI Darmstadt March 12th, 2009.
Integrated VLSI Systems EEN4196 Title: 4-bit Parallel Full Adder.
Digital Integrated Circuits© Prentice Hall 1995 Arithmetic Arithmetic Building Blocks.
Master in Microelectronics technology and Manufacturing Management E. Sicard - introducting 90nm 4. Introducing 90nm technology.
© Digital Integrated Circuits 2nd Inverter Digital Integrated Circuits A Design Perspective The Inverter Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic.
An Introduction to VLSI (Very Large Scale Integrated) Circuit Design
Technical Report High Speed CMOS A/D Converter Circuit for Radio Frequency Signal Kyusun Choi Computer Science and Engineering Department The Pennsylvania.
The development of the readout ASIC for the pair-monitor with SOI technology ~irradiation test~ Yutaro Sato Tohoku Univ. 29 th Mar  Introduction.
Experiment Electronics UMC 0.18µm radiation hardness studies Progress since last Collaboration Meeting Sven Löchner GSI Darmstadt 15 th CBM Collaboration.
Design and Assessment of a Robust Voltage Amplifier with 2.5 GHz GBW and >100 kGy Total Dose Tolerance Jens Verbeeck TWEPP 2010.
ASIC buck converter prototypes for LHC upgrades
RD53 Analog IP blocks WG : developments and plans at CPPM M. Barbero, L. Gallin Martel (LPSC), Dzahini (LPSC), D. Fougeron, R. Gaglione (LAPP), F. Gensolen,
Microelectronics User Group Meeting TWEPP 2013, Perugia, IT 26/9/2013.
BeamCal Electronics Status FCAL Collaboration Meeting LAL-Orsay, October 5 th, 2007 Gunther Haller, Dietrich Freytag, Martin Breidenbach and Angel Abusleme.
A high speed serializer ASIC for ATLAS Liquid Argon calorimeter upgrade Tiankuan Liu On behalf of the ATLAS Liquid Argon Calorimeter Group Department of.
Motivation for 65nm CMOS technology
Test structures for the evaluation of TowerJazz 180 nm CMOS Imaging Sensor technology  ALICE ITS microelectronics team - CERN.
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 6.1 EE4800 CMOS Digital IC Design & Analysis Lecture 6 Power Zhuo Feng.
SuperKEKB 3nd open meeting July 7-9, 2009 Hans-Günther Moser MPI für Physik Sensor and ASIC R&D Sensor Prototype Production: running, ASICs: Switcher,
Federico Faccio CERN/PH-MIC
Technical Report 4 for Pittsburgh Digital Greenhouse High Speed CMOS A/D Converter Circuit for Radio Frequency Signal Kyusun Choi Computer Science and.
CMOS Analog Design Using All-Region MOSFET Modeling
LPNHE - Serial links for Control in 65nm CMOS technology - 65nm CMOS - Higher density, less material, less power - Enhanced radiation hardness regular.
BUILDING BLOCKS designed at IPHC in TOWER JAZZ CMOS Image Sensor 0.18 µm process Isabelle Valin on behalf of IPHC-PICSEL group.
EE140 Final Project Members: Jason Su Roberto Bandeira Wenpeng Wang.
Irradiation results of technologies for a custom DC-DC converter F.Faccio, G.Blanchot, S.Michelis, C.Fuentes, B.Allongue, S.Orlandi CERN – PH-ESE.
- TMS - Temperature Monitoring System in Topix Olave Jonhatan INFN section of Turin and Politecnico P PANDA Collaboration Meeting December 9 th
20-NM CMOS DESIGN.
Access to 65nm Technology through CERN
منبع: & کتابMICROELECTRONIC CIRCUITS 5/e Sedra/Smith
Forward-bias operation of FZ and MCz silicon detectors made with different geometries in view of their applications as radiation monitoring sensors J.
Presentation transcript:

Circuit design with a commercial 0.13  m CMOS technology for high energy physics applications K. Hänsler, S. Bonacini, P. Moreira CERN, EP/MIC

LECC 2003Kurt Hänsler - CERN2 Outline Background Technology presentation Test module Radiation tolerance Bandgap Dual port SRAM Time to digital converter Conclusions

LECC 2003Kurt Hänsler - CERN3 Background Can we take profit from this new technology? –Radiation tolerance? –Higher functional density? –Use in high energy physics experiments? –Commercial libraries? –Costs?

LECC 2003Kurt Hänsler - CERN4 Technology presentation Technology features 0.13  m generation CMOS technology All copper technology, 4 – 8 metal levels Core supply 1.2V & 1.5V I/O voltages 2.5V & 3.3V Triple gate oxide (1.7nm, 2.2nm, 5.2nm) Non-epi p- substrate Device options Standard, low Vt, high Vt NMOS and PMOS, ZeroVt NMOS Ultra thin gate oxide NMOS and PMOS Thick oxide NMOS, PMOS and ZeroVt NMOS n+ diffusion and p+ polysilicon resistors Metal-insulator-metal precision capacitors

LECC 2003Kurt Hänsler - CERN5 Test module 5x5mm module in foundry MPW –Test structures –Basic circuit building blocks: SRAM, TDC, Bandgap, Serializer, Shift Register, AFP Design start Jul-03 Submission Nov-03 Reception Mar-04 Cooperation with RAL and Imperial College London

LECC 2003Kurt Hänsler - CERN6 Radiation tolerance: TID, 30 Mrd Linear transistors with 1.7 nm and 2.2 nm physical gate oxide thicknesses present a promising natural TID hardness. No worries for a number of environments. Linear transistors with 5.2nm gate oxide are more sensitive: careful use. Further information: K. Hänsler et al. “TID and SEE performance of a commercial 0.13  m CMOS technology” Proceedings RADECS 2003

LECC 2003Kurt Hänsler - CERN7 Radiation tolerance: SEE SEU cross section in order of magnitude of older technologies. Influence of supply voltage and TID on SEU cross section as foreseen and expected in the past. Further information: K. Hänsler et al. “TID and SEE performance of a commercial 0.13  m CMOS technology” Proceedings RADECS 2003

LECC 2003Kurt Hänsler - CERN8 Bandgap: Structure New structure required due to low supply voltage. Standard structure based on the sum of the built-in voltage of a diode and of the thermal voltage.

LECC 2003Kurt Hänsler - CERN9 Bandgap: Structure

LECC 2003Kurt Hänsler - CERN10 Bandgap: Results Reference Voltage: 0.587V Power supply sensitivity: 14mV/V Temperature sensitivity: 0.22mV/K Minimum supply voltage: 1V Current consumption: 310  1.5V

LECC 2003Kurt Hänsler - CERN11 Bandgap: Irradiation Reference voltage before irradiation: 587mV

LECC 2003Kurt Hänsler - CERN12 Bandgap: Comparison with 0.25  m 0.13  m0.25  m Die area  m  m 2 Nominal supply voltage 1.5 V2.5 V Operational supply voltage range 1.0…1.7 V1.4…2.7V Temperature sensibility of reference voltage mV/K-0.22 mV/K Nominal reference voltage V1.175 V Reference voltage variation over supply voltage range < 10 mV< 1mV

LECC 2003Kurt Hänsler - CERN13 SRAM: Structure 1.5 V supply Memory size 256x9 bits Physical size: 553  m X 129  m

LECC 2003Kurt Hänsler - CERN14 SRAM: Memory cell  2 cross-coupled inverters  2 enclosed NMOS  2 PMOS  2 PMOS pass transistors  Cell size 3.73  m X 2.58  m

LECC 2003Kurt Hänsler - CERN15 SRAM: Results All cells fully functional for supply voltages above 1.6V and frequencies up to 75 MHz. Read operation down to 0.8V Write operation: limited operation range Power consumption 25MHz –Increase rate 104  W/MHz in future: no enclosed layout, but EDAC

LECC 2003Kurt Hänsler - CERN16 SRAM: Comparison 0.25  m 0.13  m0.25  m Cell size 9.62  m 2  m 2 Nominal supply1.6 V2.5 V Access time5.1 ns4.5 ns Maximum operation frequency 75 MHz70 MHz

LECC 2003Kurt Hänsler - CERN17 TDC: Structure

LECC 2003Kurt Hänsler - CERN18 TDC: Delay Cell

LECC 2003Kurt Hänsler - CERN19 TDC: Results I

LECC 2003Kurt Hänsler - CERN20 TDC: Results II

LECC 2003Kurt Hänsler - CERN21 TDC: Results III

LECC 2003Kurt Hänsler - CERN22 Conclusions Natural radiation tolerance Higher functional density / Use in HEP experiments 3 prototypes, linear and enclosed designs, with satisfying results presented  Costs  Technology is in full production BUT still very high engineering costs  Low voltage design challenge Use of commercial library possible

LECC 2003Kurt Hänsler - CERN23 Besten Dank für Ihre Aufmerksamkeit. Grazie per la vostra attenzione. Muito obrigado pela vossa atenção. Thank you for your attention. Je vous remercie de votre attention. Acknowledgements: J. Christiansen, F. Faccio, K. Kloukinas, A. Marchioro, R. Szczygiel, G. Cervelli, E. Murer