CERN - Jérôme Masson – 21/03 March 21, 20131SRAM Design for VFAT3/GdSP - CERN.

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Presentation transcript:

CERN - Jérôme Masson – 21/03 March 21, 20131SRAM Design for VFAT3/GdSP - CERN

Outline Objectives Pointers of the issue Strategy March 21, 20132/9SRAM Design for VFAT3/GdSP - CERN

Objectives Perform a new implementation of memory modules for VFAT3/GdSP development Why? IBM CMOS 130 nm Dual Port Bypass the issue March 21, 20133/9SRAM Design for VFAT3/GdSP - CERN

Pointers of the issue VFAT2 had 2 memory modules SRAM1 SRAM2 Radiation environment Hamming encoding March 21, 20134/9SRAM Design for VFAT3/GdSP - CERN

SRAM (1/3) Divide SRAM1 … in several little modules Idea : Available memory generator for modules March 21, 20135/9SRAM Design for VFAT3/GdSP - CERN ………M_1M_n SRAM latency read ptrwrite ptr

SRAM (2/3) Memory implementation and control March 21, 2013SRAM Design for VFAT3/GdSP - CERN6/9 clk read_en write_en address data_in data_out M_1 M_1bis decoder clk LV1A write_en read_enaddress

SRAM (3/3) RECAP, first sizing Use of the memory generator Size of a memory module : 128 x 64 W = 156 µm ; L = 428 µm Total area for SRAM1 (#20 modules) Area # 1.3 mm² March 21, 20137/9SRAM Design for VFAT3/GdSP - CERN

FIFO and Hamming Encoding FIFO Hamming Encoding extra bits so extra size… March 21, 20138/9SRAM Design for VFAT3/GdSP - CERN

Thank you for paying attention March 21, 2013SRAM Design for VFAT3/GdSP - CERN9/9