Production and Testing of the DØ Silicon Microstrip Tracker Frank Filthaut University of Nijmegen / NIKHEF For the DØ Collaboration NSS-MIC, October 2000 r The DØ Run II upgrade r The Silicon Microstrip Tracker design r Detector production r Testing r Expected performance r Conclusions

2 p Addition of central axial 2T magnetic field (SC solenoid in front of calorimeter cryostat) p Extend muon chamber coverage, smaller granularity (better lepton ID) p Upgraded calorimeter, trigger, DAQ electronics DØ Run II Upgrade p Bunch spacing: from 3.5  s to 132 ns ns) p Aim: collect  2-3 fb -1 in several years p #MB interactions/crossing: ·10 32 cm -2 s -1 ) p Interaction region:  z = 25 cm

3 DØ Run II Upgrade - Tracking p B-tagging based on b lifetime (scintillating fibre tracker complemented by silicon strip detector) p Improved muon and electron (preshower detectors) identification and triggering p Charge sign determination p High-p T central physics in dense environment  redundancy p B physics, QCD studies  good forward coverage Physics requirements impacting tracker design: All these detectors use the SVX2 digital front-end chip

SMT Design Basic SMT Design: p 6 barrels p 12 F disks p 4 H disks Axial strips to be used in L2 Silicon Track Trigger (STT): r stringent requirements on barrel alignment r six-fold azimuthal symmetry Should be radiation-hard to several Mrad (from pp interactions) Totals: 793k channels, 768 modules 3.0 m 2 (of which 1.6 m 2 DS) 1.5 M wire bonds

5 SMT Design p Layers 1 (3): 12 (24) DS, DM 90º ladders produced from 6” wafers (6 chips) (barrels 1 & 6: SS axial ladders from 4” wafers: 3 chips) p Layers 2 (4): 12 (24) DS 2º ladders produced from 4” wafers (9 chips) SMT barrel cross-section: Ladder count: 72 SS DS (90º) DS (2º) SMT disks: p F disks: 12 DS ±15º wedges (8+6 chips) p H disks: 96 SS 7.5º half-wedges made into full wedges and glued back to back (2x6 chips) Wedge count: 144 F + 96 H

6 Anatomy of a Ladder p Ladders supported by “active” (cooled) and “passive” beryllium bulkheads p Ladders fixed by engaging precision notches in beryllium substrates on posts on bulkheads p Beryllium cools electronics  expect chips to operate at 25 ºC using 70% H 2 O/30% ethyl glycol mixture at –10 ºC  hottest Si point should be at 5-10 ºC (DS), 0 ºC (SS) p High Density Interconnect (HDI) tail routed out radially between outer layers p Carbon-fibre/Rohacell rails glued to sensors for structural stiffness

7 High Density Interconnect p Two-layer flex-circuit mounted directly on silicon, housing SVX chips as well as passive electronics p Kapton based, trace pitch 200  m p Connects to “low-mass” cable using Hirose connector p 9 different types for the 5 sensor types  2 for each sensor type except H disks  2 types for each ladder differ only in tail length p Laminated to beryllium substrate (total mass  X 0, of which X 0 from Si) Need 912 HDI’s 9-chip HDIH-wedge HDI

8 Ladder Production in steps (9-chip) 1. Apply pattern of non-conductive epoxy on p-side beryllium 2. Align beryllium with respect to active sensor, apply pressure and cure for 24 hr 3. Align active & passive sensors w.r.t. each other, apply wire bonds. Then use separate fixture to position carbon-fibre rails. Use conductive epoxy to ground “passive” beryllium. Cure for 24 hr 0. HDI laminated to beryllium substrates, all chips & passive components mounted and tested

9 Ladder Production in steps (9-chip) 4. Use “flip fixture” to have n-side on top 5. Apply epoxy to n-side beryllium, fold over and secure HDI. Apply pressure and cure for 24 hr. Then apply n-side Si-Si and Si-SVX wirebonds 6. Encapsulate bonds at HDI edges. Connect “active” beryllium to cable ground

10 Testing & Repairs Bonds need to be plucked Bad ground connection p Broken capacitors: cause SVX front-end to saturate, tends to affect neighbouring channels as well  pluck corresponding bonds p Bad grounding of beryllium substrates causes large pedestal structures (bad for common threshold) as well as high noise  ensure R Be-gnd < 10  (in fact now better than 1  ) p Repair broken / wrong bonds p Replace chips / repair tails damaged during processing DAQ run stand-alone from spreadsheet program (+ help from probe station, logic analyzer) to check pedestals, (selective) test charge inject, sparsification

11 Burn-in & Laser Tests Dead Channel Laser Laser Test: p Energy just < Si bandgap (atten. length  400  m  test full sensor thickness) p Find dead & noisy channels p Determine initial operating voltages (from pulse height plateau, I leak -V curve) Burn-in Test: Long-term (72 hr, 30’ between runs) test of whole ladder/wedge (conditions close to those in experiment) x-y movable laser head

12Sensors Double-sided, double-metal sensors: Sensor delivery from Micron has been slow (30% yield) mainly due to p-stop defects on mask (noise affecting  strips) Schedule problem Single-sided sensors: Sensor flatness marginal for trigger purposes (understood to be due to processing: generic) Module assembly modified to minimise problem

13Micro-discharges p Potential difference across coupling capacitor oxide layer  high fringe field at edge in silicon bulk (see KEK ) p Above certain voltage, micro-discharges (avalanche breakdown) cause burst noise inhibiting operation p Correlates with sudden increase of leakage current p Sensitive to implant-metal alignment p Worst at junction side (n + side after type inversion) p Potentially limiting factor for lifetime of detector Worry for DS sensors using integrated coupling capacitors: Example for un-irradiated detector (bias on p + -side): p + metal at ground p + metal floating

14Micro-discharges p Irradiated with neutrons, fluence  cm -2 (corresponding to several fb -1 for innermost DØ silicon layer, type inverted) p Kept at room temperature for  4 months for accelerated reverse annealing Test on irradiated DSDM detector: p-side noise n-side noise After type inversion, problem worst at n + side Different curves correspond to different p + bias (-HV) for same total bias Applying bias to both p + and n + sides, total bias limited to  V (aim to keep noise below 3 counts) Assuming a V overbias to retain high charge collection efficiency on p + side, this limits the maximum depletion voltage to  100 V  good for  4 fb -1 Noise for un-irradiated detectors  2 ADC counts

15 Production status and overall quality Detector classification: p Dead channel: laser response < 40 ADC counts p Noisy channel: (burn-in) pedestal width > 6 ADC counts (normally < 2 counts excluding coherent noise) p Grade A: less than 2.6% dead/noisy channels p Grade B: less than 5.2% dead/noisy channels Use only detector grades A,B; mechanically OK Example for 9-chip detectors (better for other detector types): DeadNoisy p All sensors delivered p All HDIs delivered p Ladder and wedge production, testing essentially complete (driven by HDI/sensor delivery) Production status:

16 Barrel Assembly in steps 1. Insert individual ladders into rotating fixture using 3D movable table 2. Manually push notches against posts (all under CMM) p Rule of thumb:  Align to 20  m (trigger)  Survey to 5  m (offline) p Precisely machined bulkheads p Barrel assembly done inside out (protect wire bonds)

17 Barrel Assembly p Layer 4 glued to bulkheads (providing structural stiffness, holding passive BH) p Thermally conductive grease applied (active BH only) for other layers First 4 barrels assembled (  4 weeks/barrel, excluding survey) 3. Secure ladder using tapered pins

18 F-Disk Assembly p F-disk assembly less critical (not included in trigger), nevertheless performed under CMM (5-10  m accuracy) p Quick process p After assembly, “central” F-disk cooling rings screwed onto active barrel bulkheads z=0 V depl HHHHHHL M L L L M All disks are not created equally! Distribution of different quality devices over disks: H/M = Micron high/medium V depl, L = Eurisys low V depl Prefer high V depl now to reach micro-discharge limit later

19 Half-cylinder assembly “Mating” of central F disks to barrels: Disk lowered on support arm, cooling ring screwed onto barrel BH Accuracy ~ 75  m in transverse plane Individual barrel-disk assemblies lowered into CF support trough Central part of first half-cylinder

20 Half-cylinder assembly Installation of end disks: End disks assembled and lowered into support trough First half-cylinder complete on 28/9 Afterwards: put on top cover, cut HDI tails to length, connect to “low-mass” cables, verify cooling circuit, test… almost done

21 Readout Electronics p For 5% occupancy, 1 kHz trigger rate: bits/s  need error rate  p Exercise readout system as much as possible before installation in experiment  10% system test using full readout chain (readout full F disk, barrel, barrel-disk assembly, H disk) p Complete readout chain (including L3 analysis, data storage) tested on several detectors Monitoring Control platform SEQSEQ SEQSEQ SEQSEQ SEQSEQ SEQSEQ SEQSEQ VRB Controller Optical Link 1Gb /s VBDVBD V R B 68k Secondary Datapath VME 3M NRZ/ CLK IB L3HOST Examine HDI Low Mass

22 Conclusions & lessons p Huge effort:  large amount of silicon  stringent constraints (alignment, material budget)  many different parts (5 sensor types, 9 HDI types), … p Now nearing (successful) completion, confident that the whole detector will be in place by 1/3/2001 startup date (even if not all electronics might be) p Think this detector should last at least ~ 4 fb -1 Good: But: p We know it will not last for all of the Tevatron Run II (current projections by beams division ~ 15 fb -1, rather than original estimate of 2 fb -1 ) p We’re thinking of our next detector! If we have the luxury to learn from our experience this time:  Abandon DS silicon sensors (radiation hardness)  Lower number of sensor/hybrid types  Attempt to automate production as much as possible We have an exciting time ahead of us!