CR-SMASH CR-SMASH for MEMS simulation on UNIX-SUN and HP The semiconductor industry is now mixing electronic circuitry with mechanical and power devices.

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Presentation transcript:

CR-SMASH CR-SMASH for MEMS simulation on UNIX-SUN and HP The semiconductor industry is now mixing electronic circuitry with mechanical and power devices. To answer such interdomain simulation needs, the best solution is using SMASH. For Cadence, Mentor Graphic, ViewLogic… design flow users, CR-SMASH package associated to ME X EL will answer the need of electronic interdomain simulation while offering simple framework interfacing. Based on a single simulation engine, CR-SMASH stands out for its accuracy and simulation speed. Used with ME X EL add-on, mechanical devices can be described directly through their partial differential equations enabling dynamical electronic simulation of the mechanical devices with their associated electronic circuitry. CR-SMASH features Input formats Verilog-HDL + SDF C language VHDL (Rel 4.0) and VHDL-AMS (pending) Spice Analog Behavioral C-based Description Partial differential equations ( ME X EL ) Main general features Composer & Silicon Architect interfacing Automatic management of mixed signal netlists Single simulation engine for logic & analog Interactive waveform interface even during simulation EMBLEM library of interdomain simulation models (electromechanical, power devices…) SUN, HP and PC-NT/95 compatible… Analog and Digital features AC, DC, noise, power-up and transcient analyses Sweep and Monte-carlo analysis Improved analog algorithms Diverse FFT analysis Laplace transform blocks Power dissipation analysis Reusable bias point Switch models for MOS simulation Toggle test for coverage analysis Load dependent delay for gates… Supported transistor models Level 0, 1, 2 and 3, BSIM 1 and 3v3 EKV, MM9, SOI, ST, AMS, ELMOS… CR-SMASH features Input formats Verilog-HDL + SDF C language VHDL (Rel 4.0) and VHDL-AMS (pending) Spice Analog Behavioral C-based Description Partial differential equations ( ME X EL ) Main general features Composer & Silicon Architect interfacing Automatic management of mixed signal netlists Single simulation engine for logic & analog Interactive waveform interface even during simulation EMBLEM library of interdomain simulation models (electromechanical, power devices…) SUN, HP and PC-NT/95 compatible… Analog and Digital features AC, DC, noise, power-up and transcient analyses Sweep and Monte-carlo analysis Improved analog algorithms Diverse FFT analysis Laplace transform blocks Power dissipation analysis Reusable bias point Switch models for MOS simulation Toggle test for coverage analysis Load dependent delay for gates… Supported transistor models Level 0, 1, 2 and 3, BSIM 1 and 3v3 EKV, MM9, SOI, ST, AMS, ELMOS… Hierarchical Spice netlisting from Composer ™, Design architect ™ … Dolphin IntegrationDolphin GmbHDolphin US Meylan - FranceDuisburg - GermanySanta Clara - USA Tel. (33) Tel. (49) Tel. 1 (408) Fax (33) Fax (49) Fax 1 (408) Composer™ is a Trade Mark of Cadence Design Architect™ is a Trade Mark of Mentor Graphics SMASH