Procedure Hopping: a Low Overhead Solution to Mitigate Variability in Shared-L1 Processor Clusters Abbas Rahimi ‡, Luca Benini †, and Rajesh Gupta ‡ ‡ CSE, UC San Diego † DEIS, Università di Bologna International Symposium on Low-Power Electronics and Design micrel.deis.unibo.it

Procedure Hopping to Mitigate Variability 2 Main Point

3 Across-wafer Frequency V CC Droop Temperature Clock actual circuit delay guardband Other uncertainty Sources of Device Variation 10% V CC, ~160˚C Temperature, 40% V TH Variations are more challenging in a many-core platform!

Sources of Variations Variation-tolerant Shared-L1 Processor Cluster 1.Process Variation → Variation-aware V DD -hopping 2.Dynamic Voltage Variation → Procedure hopping Methodology for PLV –Design time characterization –Compile time PLV metadata generation –Runtime preventive compensation Experimental Results 4 Outline

Each cluster consists of: 16 LEON-3 cores An intra-cluster shared-L1I$ An on-chip multi-banked tightly coupled data memory (TCDM) Two single-cycle logarithmic interconnections for both instruction and data sides A hardware synchronization handler module (SHM) to coordinate and synchronize cores for accessing shared data on TCDM. V DD -hopping per core. 5 Shared-L1 TCDM cluster template 4x8 cluster: 4 PEs and an 8-bank TCDM Shared-L1 Processor Clusters * * D. Melpignano, L. Benini, et al., “Platform 2012, a many-core computing accelerator for embedded SoCs: performance evaluation of visual analytics applications”, DAC’12

 Three cores (f4, f8, f9) cannot meet the target frequency of 830MHz. 6 V DD = 0.81V V DD = 0.99V VA-V DD -Hopping=( 0.81V0.99V, ) f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f V DD –hopping to Compensate Process Variation  All cores of the same cluster meet the target frequency of 830MHz. VA-V DD -hopping can accordingly tune the cores' voltage based on their delay reported by CPMs.

V DD –hopping to Compensate Process Variation 7 Every core have its own voltage domain All cores work with the same frequency V DD -hopping tunes the voltage of each core based on CMP. Each core increases voltage if its delay is high. The process variation is compensated but, cluster will have various Voltage/Temperature-islands! f f f f f f f f f f f f f f f f

The IR-drop of execution of FIR on cores with various operating corners. FIR does not face any voltage emergency (IR-drop < 4%) at the corners with voltages of 0.81V- 0.9V due to their lower power densities. 8 (Vol., Temp.)0.99V, 125C0.90V, 25C0.81V, 125C0.81V, -40C Power density0.66 μW/μm μW/μm μW/μm μW/μm 2 Max IR-drop44 mV< 35 mV< 31 mV Fast Dynamic IR-drop within Cluster

Procedure hopping to Compensate Voltage Variation 9 Procedure hopping facilitates fast and proactive migration of procedures within a cluster to prevent voltage variation thanks to shared I$ and TCDM resources. Each procedure hops from one core to another if it causes voltage variation.

Sources of Variations Variation-tolerant Shared-L1 Processor Cluster 1.Process Variation → Variation-aware V DD -hopping 2.Dynamic Voltage Variation → Procedure hopping Methodology for PLV –Design time characterization –Compile time PLV metadata generation –Runtime preventive compensation Experimental Results 10 Outline

Procedure-level Vulnerability (PLV) The notion of PLV to fast dynamic voltage variation is defined. The design time stage analyzes the dynamic voltage droops/rises for every Proc X under full operating conditions  generating PLV x metadata. 11 int Proc X (…) { … } (V i,T j ) Core i Observe IR-drops (V,T)PLV X V1,T10.75 V2,T20.35 V3,T30.01 ……

Characterization of PLV to IR-drop: Compile time + Runtime 12 At compile time, PLV x metadata of Proc X is attached to the procedure. During runtime, the discretized (V,T) point to the corresponding characterized PLV metadata to assess the vulnerability of Proc X at the current (V,T). If PLV x ≥ PLV_threshold, the Proc X will be hopped from caller core to a favor callee core.

Sources of Variations Variation-tolerant Shared-L1 Processor Cluster 1.Process Variation → Variation-aware V DD -hopping 2.Dynamic Voltage Variation → Procedure hopping Methodology of PLV –Design time characterization –Compile time PLV metadata generation –Runtime preventive compensation Experimental Results 13 Outline

Max Voltage Variation Across Corners and Procedures 14 (Vol., Temp.)a2timFIRIFFTbitmnpcachebIDCTmatrixpntrchPWMsspeedtblookttsprk 0.99V, 125°C V, 25°C V, 125°C V, -40°C Max voltage droop (%) Most of procedures running at cores with 0.99V have voltage emergencies. At 0.9V, only four procedures (IFFT, IDCT, matrix, ttsprk) face the voltage emergencies. No voltage emergency at 0.81V. Procedure hopping avoids the voltage emergency for all procedures by hopping them form a high-voltage core to a low- voltage core.

Cost of Procedure Hopping The total roundtrip overhead of the hopping a procedure from the caller core and returning the results from the callee core is less than 800 cycles. This overhead is less than 1% of the total cycles needed to execute any of the characterized procedures in EEMBC benchmark. During the procedure hopping no voltage emergency can occur even at (0.99V,125˚C), neither in the caller nor the callee core. 15 Caller hopping Caller not hopping Callee service Callee no service Latency218 cycles88 cycles575 cycles342 cycles Voltage droop1.3%0.6%2.9%1.8%

Conclusion The notion of procedure-level vulnerability to fast dynamic voltage variation is defined. Based on PLV metadata, a fully-software low-cost procedure hopping technique is proposed which guarantees the voltage emergency-free migration of all procedures, fast and proactively enough within a shared-L1 processor cluster. Full post-P&R results in 45nm TSMC technology confirms that the procedure hopping avoids the voltage emergency across a variability-affected cluster, while imposing only an amortized cost of less than 1% latency for any of the characterized embedded procedures. 16

17 Thank you! Acknowledgment NSF Variability Expedition ERC Multitherman Project

HW/SW Collaborative Architecture to Support Intra-cluster Procedure Hopping 18 The code is easily accessible via the shared-L1 I$. The data and parameters are passed through the shared stack in TCDM. A procedure hopping information table (PHIT) keeps the status for a migrated procedure.

Intra-procedure Peak Power Variation Maximum of 1.28× intra-corner peak power variation occurs between IFFT and tblook procedures at (0.81V,125C). Maximum inter-corner peak power variation is 3.5× for FIR. Maximum of 4.1× peak power variation across corners and procedures, a2time at (0.81V,-40C), and IFFT at (0.99V,125C). 19