doc.: IEEE /0261r0 Submission September 2008 Siaud.I,Benko.J, France Telecom R&D Slide 1 Comment # 698: Binary Interleaving implementation IEEE P Wireless RANs Date: Authors: Notice: This document has been prepared to assist IEEE It is offered as a basis for discussion and is not binding on the contributing individual(s) or organization(s). The material in this document is subject to change in form and content after further study. The contributor(s) reserve(s) the right to add, amend or withdraw material contained herein. Release: The contributor grants a free, irrevocable license to the IEEE to incorporate material contained in this contribution, and any modifications thereof, in the creation of an IEEE Standards publication; to copyright in the IEEE’s name any IEEE Standards publication even though it may include portions of this contribution; and at the IEEE’s sole discretion to permit others to reproduce in whole or in part the resulting IEEE Standards publication. The contributor also acknowledges and accepts that this contribution may be made public by IEEE Patent Policy and Procedures: The contributor is familiar with the IEEE 802 Patent Policy and Procedures including the statement "IEEE standards may include the known use of patent(s), including patent applications, provided the IEEE receives assurance from the patent holder or applicant with respect to patents essential for compliance with both mandatory and optional portions of the standard." Early disclosure to the Working Group of patent information that might be relevant to the standard is essential to reduce the possibility for delays in the development process and increase the likelihood that the draft publication will be approved for publication. Please notify the Chairhttp://standards.ieee.org/guides/bylaws/sb-bylaws.pdf Carl R. StevensonCarl R. Stevenson as early as possible, in written or electronic form, if patented technology (or technology under patent application) might be incorporated into a draft standard being developed within the IEEE Working Group. If you have questions, contact the IEEE Patent Committee Administrator at >

doc.: IEEE /0261r0 Submission September 2008 Siaud.I,Benko.J, France Telecom R&D Slide 2 Motivations and Outline Analysis of IEEE binary interleaving process and additional information following comment#698

doc.: IEEE /0261r0 Submission September 2008 Siaud.I,Benko.J, France Telecom R&D Slide 3 + IFFT Binary interleaving FEC coding sub-carrier Modulation Multipath channel AWGN Pilot insertion S/P Tcp Insertion X X X N FFT X Information binary Source Guard sub-carriers Data scrambingl Puncturing sub-carrier Interleaving In(k) Kd=1440 (DS) Kd=  1624 (US) Ki bits i={1,..32} {pm,qm,jm} m={1,..,9} permutation rules selection Overall interleaving process in IEEE802.22

doc.: IEEE /0261r0 Submission September 2008 Siaud.I,Benko.J, France Telecom R&D Slide 4 IEEE Interleaving process (1/2) A single stage interleaver to generate desired interleaving pattern An iterative loop into the stage : less complex than multi-stage interleaver Algebraic implementation with 2 modulo operations/ per iteration {pm,qm,jm}interleaving parameters A single stage  A single memory buffer Interleaving processing K i : interleaving size {p m, q m, j m }: interleaving parameters Ki: j=1 j=j+1 J<Jm+1 Desired interleaving pattern

doc.: IEEE /0261r0 Submission September 2008 Siaud.I,Benko.J, France Telecom R&D Slide 5 IEEE Interleaving process (2/3) 9 Common interleaving parameters {pm,qm,jm} to generate 32 interleaving patterns Coded BlockInterleaver Parameters K ( bits)pqj Coded BlockInterleaver Parameters K ( bits)pqj

doc.: IEEE /0261r0 Submission September 2008 Siaud.I,Benko.J, France Telecom R&D Slide 6 IEEE Interleaving process (3/3) 9 Common interleaving parameters {pm,qm,jm} to generate 32 interleaving patterns Solution 1 : Allocation of a dedicated memory to register 32 interleaving patterns Solution 2 : Direct generation of interleaving pattern –2 embedded modulo operations in an iterative loop to generate Ki coefficients with

doc.: IEEE /0261r0 Submission September 2008 Siaud.I,Benko.J, France Telecom R&D Slide 7 Direct generation of interleaving pattern Basic operator : A_in P -(k+(P.A_in)) (1 clock cycle) KP  +k+q.p.(V1) (1 clock cycle) Modulo K (4 clock cycles) V1 QKK Modulo K (4 clock cycles) A_out Latency = 10 clock cycles ( one iteration) Modulo operation (reciprocal multiplication) Ex. [x] K, K= 2304 size : 1/2304 = Ox1C71C (Coded on 20 bits) (Fractional number as sum of 1/2, (½)^2,(½)^3 etc...) 1. X1 = X * Ox1C71C : multiplication 2. X2 = X1 >> 20 : Shift right by 20 positions gives the quotient 3. X3 = X - (X2 * 2304) : remainder Parameters One iteration operator (10 clock cycles) 12 k K_delay A_in k A_out K_delay clock

doc.: IEEE /0261r0 Submission September 2008 Siaud.I,Benko.J, France Telecom R&D Slide 8 Full pattern generation Solution 1 : Duplication of basic operator, j=1, 2, 3 (copies) One iteration operator k I(k) J Solution 2 : Re-use of the same operator One iteration operator k –High data rate but 3 times basic complexity Clock(k) Clock(3k) I(k) J –Reduced complexity –Upto 3 times clock required –Technology dependant

doc.: IEEE /0261r0 Submission September 2008 Siaud.I,Benko.J, France Telecom R&D Slide 9 Complexity figures Basic operator implemented in FPGA –Altera Stratix EP1S80 target component –130 Logic elements –72 bits memory –190 MHz clock (sufficient for data-rates) To be compared to the ROM-based solution –Technology dependant –~ 360,000 bits