CSE477 L24 RAM Cores.1Irwin&Vijay, PSU, 2002 CSE477 VLSI Digital Circuits Fall 2002 Lecture 24: RAM Cores Mary Jane Irwin ( ) [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

CSE477 L24 RAM Cores.2Irwin&Vijay, PSU, 2002 Review: Basic Building Blocks  Datapath l Execution units -Adder, multiplier, divider, shifter, etc. l Register file and pipeline registers l Multiplexers, decoders  Control l Finite state machines (PLA, ROM, random logic)  Interconnect l Switches, arbiters, buses  Memory l Caches (SRAMs), TLBs, DRAMs, buffers

CSE477 L24 RAM Cores.3Irwin&Vijay, PSU, 2002 Review: Read-Write Memories (RAMs)  Static – SRAM l data is stored as long as supply is applied l large cells (6 fets/cell) – so fewer bits/chip l fast – so used where speed is important (e.g., caches) l differential outputs (output BL and !BL) l use sense amps for performance l compatible with CMOS technology  Dynamic – DRAM l periodic refresh required l small cells (1 to 3 fets/cell) – so more bits/chip l slower – so used for main memories l single ended output (output BL only) l need sense amps for correct operation l not typically compatible with CMOS technology

CSE477 L24 RAM Cores.4Irwin&Vijay, PSU, 2002 Review: 4x4 SRAM Memory A0A0 Row Decoder !BL WL[0] A1A1 A2A2 Column Decoder sense amplifiers write circuitry BL WL[1] WL[2] WL[3] bit line precharge 2 bit words clocking and control enable read precharge BL[i]BL[I+1]

CSE477 L24 RAM Cores.5Irwin&Vijay, PSU, transistor SRAM Cell !BLBL WL M1 M2 M3 M4 M5 M6Q !Q

CSE477 L24 RAM Cores.6Irwin&Vijay, PSU, 2002 SRAM Cell Analysis (Read) !BL=1 BL=1 WL=1 M1 M4 M5 M6 Q=1 !Q=0 C bit Read-disturb (read-upset): must carefully limit the allowed voltage rise on !Q to a value that prevents the read-upset condition from occurring while simultaneously maintaining acceptable circuit speed and area constraints

CSE477 L24 RAM Cores.7Irwin&Vijay, PSU, 2002 SRAM Cell Analysis (Read) !BL=1 BL=1 WL=1 M1 M4 M5 M6 Q=1 !Q=0 C bit Cell Ratio (CR) = (W M1 /L M1 )/(W M5 /L M5 ) V !Q = [(V dd - V Tn )(1 + CR  (CR(1 + CR))]/(1 + CR)

CSE477 L24 RAM Cores.8Irwin&Vijay, PSU, 2002 Read Voltages Ratios V dd = 2.5V V Tn = 0.5V

CSE477 L24 RAM Cores.9Irwin&Vijay, PSU, 2002 SRAM Cell Analysis (Write) !BL=1 BL=0 WL=1 M1 M4 M5 M6 Q=1 !Q=0 Pullup Ratio (PR) = (W M4 /L M4 )/(W M6 /L M6 ) V Q = (V dd - V Tn )  ((V dd – V Tn ) 2 – (  p /  n )(PR)((V dd – V Tn - V Tp ) 2 )

CSE477 L24 RAM Cores.10Irwin&Vijay, PSU, 2002 Write Voltages Ratios V dd = 2.5V |V Tp | = 0.5V  p /  n = 0.5

CSE477 L24 RAM Cores.11Irwin&Vijay, PSU, 2002 Cell Sizing  Keeping cell size minimized is critical for large caches  Minimum sized pull down fets (M1 and M3) l Requires minimum width and longer than minimum channel length pass transistors (M5 and M6) to ensure proper CR l But sizing of the pass transistors increases capacitive load on the word lines and limits the current discharged on the bit lines both of which can adversely affect the speed of the read cycle  Minimum width and length pass transistors l Boost the width of the pull downs (M1 and M3) l Reduces the loading on the word lines and increases the storage capacitance in the cell – both are good! – but cell size may be slightly larger

CSE477 L24 RAM Cores.12Irwin&Vijay, PSU, T-SRAM Layout V DD GND Q Q WL BL M1 M3 M4M2 M5M6

CSE477 L24 RAM Cores.13Irwin&Vijay, PSU, 2002 Multiple Read/Write Port Cell WL2 BL2 !BL2 M7M8 !BL1 BL1 WL1 M1 M2 M3 M4 M5M6Q!Q

CSE477 L24 RAM Cores.14Irwin&Vijay, PSU, x4 DRAM Memory A0A0 Row Decoder BL WL[0] A1A1 A2A2 Column Decoder sense amplifiers write circuitry WL[1] WL[2] WL[3] bit line precharge 2 bit words BL[0]BL[1]BL[2]BL[3] clocking, control, and refresh enable read precharge

CSE477 L24 RAM Cores.15Irwin&Vijay, PSU, Transistor DRAM Cell M1 M2 M3 X BL1 BL2 WWL RWL XV dd -V t BL1 V dd WWL write RWLreadBL2 V dd -V t VV No constraints on device sizes (ratioless) Reads are non-destructive Value stored at node X when writing a “1” is V WWL - V tn CsCs

CSE477 L24 RAM Cores.16Irwin&Vijay, PSU, T-DRAM Layout BL2BL1GND RWL WWL M3 M2 M1

CSE477 L24 RAM Cores.17Irwin&Vijay, PSU, Transistor DRAM Cell M1 X BL WL XV dd -V t WL write “1” BL V dd Write: C s is charged (or discharged) by asserting WL and BL Read: Charge redistribution occurs between C BL and C s CsCs read “1” V dd /2 sensing Read is destructive, so must refresh after read C BL

CSE477 L24 RAM Cores.18Irwin&Vijay, PSU, T DRAM Cell

CSE477 L24 RAM Cores.19Irwin&Vijay, PSU, 2002 DRAM Cell Observations  DRAM memory cells are single ended (complicates the design of the sense amp)  1T cell requires a sense amp for each bit line due to charge redistribution read  1T cell read is destructive; refresh must follow to restore data  1T cell requires an extra capacitor that must be explicitly included in the design  A threshold voltage is lost when writing a 1 (can be circumvented by bootstrapping the word lines to a higher value than V dd )

CSE477 L24 RAM Cores.20Irwin&Vijay, PSU, 2002 Next Lecture and Reminders  Next lecture l Peripheral memory circuits -Reading assignment – Rabaey, et al, 12.3  Reminders l Project final reports due December 5 th l Final grading negotiations/correction (except for the final exam) must be concluded by December 10 th l Final exam scheduled -Monday, December 16 th from 10:10 to noon in 118 and 121 Thomas