CMOS Technology Scaling
Moore’s law “Cramming more Components onto Integrated Circuits” Gordon E. Moore, Electronics 1965, p “VLSI: some fundamental challenges” Moore, IEEE Spectrum 1970, p.30. “Moore’s law governs the Silicon revolution” Bandyopadhyay, Proc. of IEEE, 1998, p.78 Gordon Moore was Ph.D. in Chemistry Interdisciplinary barriers in Science and Technology are imaginary ! Moore co-founded Intel and proved his vision
IEEE J. Solid State Circuits, Vo. 9(5), p.256, 1974
Typical Scaling Scenario 1974 : 5 m Technology, Vdd = 10V 1984 : 1 m Technology, Vdd = 5V 1994 : 0.35 m Technology, Vdd = 3.5V 2004 : 90nm Technology, Vdd = 1V 2014 : 22nm Technology, Vdd = 0.75V
Constant Electric Field Scaling Primary scaling factors: Tox, L, W, Xj (all linear dimensions)1/K Na, Nd (doping concentration)K Vdd (supply voltage)1/K Derived scaling behavior of transistor: Electric field1 Ids1/K Capacitance1/K Derived scaling behavior of circuit: Delay (CV/I)1/K Power (VI)1/K 2 Power-delay product1/K 3 Circuit density ( 1/A)K 2 Technology scaling Scaling factor K > 1
Constant Voltage Scaling Primary scaling factors: Tox, L, W, Xj (all linear dimensions)1/K Na, Nd (doping concentration)K 2 Vdd (supply voltage)1 Derived scaling behavior of transistor: Electric fieldK IdsK Capacitance1/K Derived scaling behavior of circuit: Delay (CV/I)1/K 2 Power (VI)K Power-delay product1/K Circuit density ( 1/A)K 2 Technology scaling Scaling factor K > 1
Generalized Scaling Primary scaling factors: Tox, L, W, Xj (all linear dimensions)1/K Na, Nd (doping concentration) K Vdd (supply voltage) /K Derived scaling behavior of transistor: Electric field Ids 2 /K Capacitance1/K Derived scaling behavior of circuit: Delay (CV/I)1/ K Power (VI) 3 /K 2 Power-delay product 2 /K 3 Circuit density ( 1/A)K 2 Technology scaling Scaling factor K > 1
Non Scaling Factors Bandgap of Silicon Eg=1.12eV Thermal voltage kT/q Mobility degradation Increasing doping and electric field Velocity saturation Parasitic s/d resistance Process tolerance