WP4 – Optical Processing Sub-System Development Start M06, finish M30 UCC lead Plans for next 6 months: –Complete assembly of integrated hybrid circuits.

Slides:

Advertisements

Similar presentations

MonolithIC 3D Inc., Patents Pending MonolithIC 3D ICs October MonolithIC 3D Inc., Patents Pending.

Advertisements

© 2008 Silicon Genesis Corporation. All rights reserved. SiGen Equipment & Applications SiGen Equipment & Applications.

Silicon-Organic hybrid Fabrication platform for Integrated circuits Kick-off Meeting 01/08/2010 Partner Presentations - UKA.

Copyright © 2014 John Wiley & Sons, Inc. All rights reserved.

MEMS and PLC ee290f J Provine Overview Introduction & Motivation PLC components (AWG) MEMS components Desired System Integration technique.

INTEGRATED CIRCUITS Dr. Esam Yosry Lec. #6.

All-Optical Header Recognition M. Dagenais Department of Electrical and Computer Engineering, University of Maryland, College Park, MD 20742, USA

MonolithIC 3D  Inc. Patents Pending 1 The Monolithic 3D-IC A Disruptor to the Semiconductor Industry.

Physical Design Outline –What is Physical Design –Design Methods –Design Styles –Analysis and Verification Goal –Understand physical design topics Reading.

Evanescent fields Professor Viviana Vladutescu. What Everyone Needs to Know About Evanescent Fields Almost four hundred years ago, Newton used a prism.

Agilent Technologies Optical Interconnects & Networks Department Photonic Crystals in Optical Communications Mihail M. Sigalas Agilent Laboratories, Palo.

11/8/2004EE 42 fall 2004 lecture 291 Lecture #29 CMOS fabrication, clocked and latched circuits Last lecture: PMOS –Physical structure –CMOS –Dynamic circuits.

Photo courtesy NOAO, taken with LBNL fully depleted CCD Optical Characterization of 1.7  m NIR Detectors for SNAP M. Brown (Michigan), J. Balleza (IDTL),

Digital Circuit Implementation. Wafers and Chips  Integrated circuit (IC) chips are manufactured on silicon wafers  Transistors are placed on the wafers.

3D chip and sensor Status of the VICTOR chip and associated sensor Bonding and interconnect of chip and sensor Input on sensor design and interconnection.

Phase Change on Reflection To understand interference caused by multiple reflections it is necessary to consider what happens when a light wave moving.

Lecture 18 Chapter XI Propagation and Coupling of Modes in Optical Dielectric Waveguides – Periodic Waveguides Highlights (a) Periodic (corrugated) WG.

WP4 – Optical Processing Sub-System Development Start M06, finish M30 UCC lead Plans for next 6 months: –Begin firmware/control work –Focus on initial.

SLS Optics Limited Manufacturer of Quality Optical Components ISO 9001:2000.

Waveguide High-Speed Circuits and Systems Laboratory B.M.Yu High-Speed Circuits and Systems Laboratory 1.

PHASED: a Faster, Smarter & More Affordable Analysis Device - Update U.Bonne, J.Detry, R.Higashi, K.Newstrom-Peitso, H.Pham,

Some of the applications of Photonic Crystals (by no means a complete overview) Prof. Maksim Skorobogatiy École Polytechnique de Montréal.

1 WP3 Bi-Weekly Meeting Activities at Liverpool 1.Evaluation of Compact DCDC converter Designed to match up to an ABC130 module 2.Status of FIB’d hybrid/module.

Coupling light into a space-based microspectrograph Emma Lindley Supervised by Joss Bland-Hawthorn and Sergio Leon-Saval.

1 Hi-Lumi WP3 meeting Update on the Q1 to D1 cryostat Jan 28, 2014  Outline  Cryostat cross section options  Elliptical interconnect.

Interconnect Focus Center e¯e¯ e¯e¯ e¯e¯ e¯e¯ IWSM 2001Sam, Chandrakasan, and Boning – MIT Variation Issues in On-Chip Optical Clock Distribution S. L.

High speed silicon Mach-Zehnder modulator

The Chicago Half of Champ

Dummy and Pad Chips Needed for various activities (interconnection tests, mass tests, assembly,…) Production of masks, processing, thinning and dicing.

-1- Elias Athanasopoulos, ICS-FORTH Software Modeling WP3 Software Modelling WISDOM Simulator Elias Athanasopoulos*, Antonis Krithinakis, George Kopidakis.

Active Pixel Sensors in Nuclear Medicine Imaging RJ Ott, N Evans, P Evans, J Osmond, A Clark, R Turchetta Physics Department Institute of Cancer Research.

WISDOM WP6 Manufacturability, Scalability and Functionality Study Start M0, End M35 WP leader is CIP Objectives –Assessment of manufactureability of the.

CORPORATE INSTITUTE OF SCIENCE & TECHNOLOGY, BHOPAL DEPARTMENT OF ELECTRONICS & COMMUNICATIONS NMOS FABRICATION PROCESS - PROF. RAKESH K. JHA.

Hybrid Mechanical/Thermal Design Ray Thompson / Manchester FP420 meeting Torino 11/12 July 06.

ADVANCED HIGH DENSITY INTERCONNECT MATERIALS AND TECHNIQUES DIVYA CHALLA.

A METHOD FOR OBTAINING THE SOLUTIONS OF OPTICAL RIB WAVEGUIDES Çağatay ULUIŞIK.

MIT Lincoln Laboratory kickoff-1 PWW 4/7/2000 Via Topology for 3-D Integration 7 April 2000 Peter W. Wyatt and Paul V. Davis

WISDOM meeting 29/01/07 Photonic Systems Group Tyndall National Institute R.J. Manning R.P. Webb, X.Yang, R. Giller Tyndall National Institute/University.

WISDOM WP6 Manufacturability, Scalability and Functionality Study Start M0, End M35 WP leader is CIP Objectives –Assessment of manufacturability of the.

Introduction to Silicon Processing Dr Vinod V. Thomas SMIEEE Ref: Section 2.2 ASICs : MJS Smith.

Atsushi Taketani 2005/06/03 VTX meeting 1 PIXEL BUS status 1.Circuit design 2.Design rule and design 3.Schedule.

DOE CD-2/3a Review of the BTeV Project – December 14-16, BTeV Pixel Detector Pixel Module Assembly and Half-Plane Assembly Guilherme Cardoso James.

1ICC Proprietary MEMS DEVICE WAFER LEVEL PACKAGING TECHNICAL PRESENTATION Customer Device Wafer.

Status report Pillar-1: Technology. The “Helmholtz-Cube” Vertically Integrated Detector Technology Replace standard sensor with: 3D and edgeless sensors,

1 Coming - Embedded Active Components! How Does IPC Respond? TAEC Meeting, Minneapolis October 24, 2004 Denny Fritz.

Workshop How to make a PCB

Utah Nanofab Design Review Meeting Device Architecture (Top View Layout and Layer Cross Section) Recipes & Settings Standard Concept Equipment & Tools.

Nanotechnologies for Electronics

Integrated Circuits.

Practical advices for using TCT (mostly for Particulars setups)

3-D IC Fabrication and Devices

10 Gbps Transimpedance Amplifier and Laser Driver in 0.18 um CMOS

Hybrid Pixel R&D and Interconnect Technologies

Status of the CERN chopper.

High-Speed Optical Interconnections on Electrical Boards Using Fully Embedded Thin-Film Active Optoelectronic Devices Sang-Yeon Cho Department of Electrical.

Chapter 1 & Chapter 3.

INTRO TO TDM AND BUM TDM – Top Down Manufacturing

Alternative Bragg Fibers

INTRO TO TDM AND BUM TDM – Top Down Manufacturing

Quiz_03 2-slits interference, Phasor, thin film interference

LITHOGRAPHY Lithography is the process of imprinting a geometric pattern from a mask onto a thin layer of material called a resist which is a radiation.

Directly Modulated OEIC-WC (1st Generation – Task Area 3)

Broadband Lateral Tapered Structures for Improved Bandwidth and Loss Characteristics for All-Optical Wavelength Converters Xuejin Yan, Joe Summers, Wei.

Applications for photonics are everywhere

Broadband Lateral Tapered Structures for Improved Bandwidth and Loss Characteristics for All-Optical Wavelength Converters Xuejin Yan, Joe Summers, Wei.

High harmonic generation in a large-volume capillary for seeding of free-electron lasers Siew Jean Goh.

Thin Film Applications

TASK 1 Monolithically Integrated Mach-Zehnder Interferometer Wavelength Converter and Widely-Tunable Laser in InP Milan L. Mašanović, Vikrant Lal, Jonathon.

Design and fabrication of a wafer-scale organic printed photonic chip

PiezoMEMS Foundry to Support Research Projects

Presentation transcript:

WP4 – Optical Processing Sub-System Development Start M06, finish M30 UCC lead Plans for next 6 months: –Complete assembly of integrated hybrid circuits –Design, fab & assemble versions with integrated delay loops using feedback from 1 st versions

WISDOM WP4 CIP Activity Fabrication of integrated pattern matching motherboards Fabrication of self-correcting daughterboards Fabrication of band-gap shifted 3mm SOAs Fabrication of substrate free thin film filters

Circuit Schematics Using existing pattern matching circuit as template, custom hybrid version will initially be split into two parts and use fibre as the interconnect Stage 1 hybrid

Circuit Schematics (2) Half of pattern matching circuit refined with inclusion of on chip preamplifiers, tuneable splitters and taps, and thin film filters 10ps

Motherboard Circuit layout Real motherboard

New Daughterboards Self correcting daughterboard designs 2mm and 3mm versions

3mm SOAs MQW redesign –Shift band-edge to shorter wavelengths –Larger phase modulation, smaller amplitude modulation in C-band Devices fabricated and tested by UCC

Thin Film Filter Stress balanced TFF design –Substrate removed post deposition –70 layer stack –20-30 micron thick –Filter inserted directly into slot cut in waveguides

Next 6 months WP4 will extend beyond M30 – probably out to M36 (assuming 6 month extension to project) Assemble current pattern matching circuits & test Design and fab integrated versions using feedback from 1 st tests (new motherboards)