August 06, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology KM3NeT CLBv2 1

August 06, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology With higher TDC rates in rare conditions… Bad Network Interface Card! UDP Length error: 2

August 06, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology SVN now accommodates KC705, CLBv2.1 and CLBv2.2 designs (via generics). SVN version 1023 CLBv2.2 “only” has 4 DIP switches so for uniformity all designs, DIP: 1.UDP Test Packet Generator IPMUX(2) 2.UDP Test Packet Generator IPMUX(3) 3.UDP Test Packet Generator IPMUX(2) continuously 4.IRQ0 Top Level CLB design 3

August 06, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology Sometimes USB port only shows one USB entry after power-up. Need to unplug and plug the USB connector to have both USB ports available. CLBV2.2 4

August 06, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology 1. Loopback 2. Implement PRBS (Generator and Checker) 3. Tx Enable All default into the proper position after power-up and reset. This involves: ◦ adding some bits in register (MDIO MCR, part of WR “ep_pcs_tbi_mdio_wb.vhd”) => done! ◦ adding functionality to WR-LM32 embedded software (plus interface to LM32_2 nd )  Added bits in MDIO Control Register:  24:22 = tx_prbs_sel(2:0)  21 = sfp_tx_disable  20 = sfp_los  19 = sfp tx fault  18:16 = loopback (2:0)  Note that RX_PRBS_ERR_CNT is only accessible via the Dynamic Reconfiguration Port and therefore RXPRBSSEL, RXPRBSCNTRESET are not implemented. Request from Optical Network (Gerard, Jan Willem) 5

August 06, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology XADC okay! Note: freezer spray got the FPGA min temperature down to C XADC interface 6

August 06, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology No matter if you unplug Tx or Rx fiber, the WR link goes down. Probably due to WR Link State Machine => study Unplug TX fiber (minic SFP laser off wavelength) 7 TX RX

August 06, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology Monitor Kintex7 PHY signals (wr_gtx_phy_kintex7.vhd): 1.txpll_lockdet => always ‘1’ 2.tx_rst_done => always ‘1’ 3.rxpll_lockdet => pulse low 9 us when either Tx or Rx unplugged 4.rx_rst_done => pulse low 9 us when either Tx or Rx unplugged Pulse due to WR software that resets the PHY during initialization under control of the WR link startup state machine. WR software needs revision! This is tricky since it will affect the reset and startup procedures of various functions (including locking of PLL’s etc.). This task should be assigned manpower! Unplug TX fiber 8

August 06, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology Synthesis result of the current sources differs. ◦ XST okay ◦ Precision fails Different behavior for TDC and State Machine output data. Cause… ? To be investigated! XST versus Precision 9

August 06, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology Monitoring channel (proposal) 10 Hits-0 Hits-30 TDC stmachine (2) Clear on “timeslice_start” Latch on “timeslice_start” LM32DPRAM LM32 IPMUX Ch-2 Ch-1 Ch-0 AES TDC Ch-3 Test Start register transfer on “timeslice_start” timeslice_start IRQ Currently connected to a dummy ◦ Monitoring each time slice: 1.A set of hardware writable registers (i.e. snapshot of the TDC hits counters) 2.A slice of DPRAM accessible for the LM32_2 nd Busy Clr Set

August 06, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology At the start of time slice “n”: 1. The state machine takes a snapshot of the TDC hit counters (freeing the counters for the current time slice ‘n’). The latched information are the hit counts for ‘n-1’. 2. The LM32_2 nd software (IRQ routine) had time during time-slice ‘n-1’ to prepare monitoring data in DPRAM. 3. One (small) UDP packet can be assembled fast (one or two clock cycles per register or DPRAM access by stmachine channel 2) since all data to transfer is available. 4. An “busy” bit in a stmachine register which signals that the UDP packet assembly completed may be helpful (set with “timeslice_start”, clear after stmachine-2 transfer complete). The LM32_2 nd can check this bit in its IRQ-routine to see if all data in the DPRAM section is transferred and the section is free for access of new values. Monitoring channel (proposal) 11

August 06, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology Revision of TDR Moved: ◦ “KM3NeT_ELEC_WD_2013_009_CLBv2_Register_description _PJ_VvB_DC_VK_Draft.docx” from Google Docs so it is no longer in the claws of Google who mutilates the document markup (the hell with Google Docs!) ◦ Now Google Docs “KM3NeT_ELEC_WD_2013_009_CLBv2_Register_description _PJ_VvB_DC_VK_Draft.docx” only contains a link to the SVN document: sign/clb/doc/KM3NeT_ELEC_WD_2013_009_CLBv2_Register_ description_PJ_VvB_DC_VK_Draft.docx sign/clb/doc/KM3NeT_ELEC_WD_2013_009_CLBv2_Register_ description_PJ_VvB_DC_VK_Draft.docxDocumentation 12

August 06, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology Backup slides 13