1 (Based on text: David A. Patterson & John L. Hennessy, Computer Organization and Design: The Hardware/Software Interface, 3 rd Ed., Morgan Kaufmann, 2007) Instructions - Addressing Modes

2 COURSE CONTENTS Introduction è Instructions Computer Arithmetic Performance Processor: Datapath Processor: Control Pipelining Techniques Memory Input/Output Devices

3 Overview of MIPS Simple instructions all 32 bits wide Very structured, no unnecessary baggage Only three instruction formats Addresses are not 32 bits How do we handle this with load and store instructions op rs rt rdshamtfunct op rs rt 16 bit address op 26 bit address RIJRIJ

4 Addresses in Branches and Jumps Instructions: bne $t4,$t5,Label Next instruction is at Label if $t4 ≠ $t5 beq $t4,$t5,Label Next instruction is at Label if $t4=$t5 j Label Next instruction is at Label Formats: op rs rt 16 bit address op 26 bit address IJIJ

5 Addresses in Branches Instructions: bne $t4,$t5,Label Next instruction is at Label if $t4 ≠ $t5 beq $t4,$t5,Label Next instruction is at Label if $t4=$t5 Formats: Could specify a register (like lw and sw) and add it to address Use Instruction Address Register (PC = program counter) Most branches are local (principle of locality) Jump instructions just use high order bits of PC Address boundaries of 256 MB op rs rt 16 bit address I

6 Addressing Modes Register addressing Register addressing operand is in a register, e.g. add $s1, $s2, $s3 Base or displacement addressing Base or displacement addressing operand at memory location [register + constant (base)] e.g. 2nd operand in lw $t0, 200($s1) Immediate addressing Immediate addressing operand is a constant within instruction e.g. 3rd operand in addi $s1, $s2, 10 PC-relative addressing PC-relative addressing address = PC (+4) + constant in instruction (*4) e.g. 3rd operand in bne $s0, $s1, Exit Pseudodirect addressing Pseudodirect addressing address = PC upper bits concatenated with 26-bit address in inst.

7 Addressing Modes

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9 Other Issues MIPS assembler accepts this pseudoinstruction even though it is not found in MIPS architecture: move $t0, $t1 #$t0  $t1 it translates it to: add $t0, $zero, $t1 Other pseudoinstructions: mult, blt, bge, etc. Assembler keeps track of addresses of labels in symbol table Details of assembler, linker, & loader are given in Appendix A Details of MIPS instruction set & architecture in Appendix A % frequency of instruction execution

10 Instruction Set Architecture Classes Use of accumulator (a default register): 1 address instruction; e.g. add A: acc  acc + mem[A] e.g. EDSAC, IBM 701, DEC PDP-8, MC 6800, Intel 8008 Use of stack: 0 address instruction; e.g. add: top(stack)  top(stack) + next_top(stack) Use of general purpose registers: 2 address instruction; e.g. add A, B:A  A + B 3 address instruction; e.g. add A,B,C:A  B + C load/store (reg/reg): e.g. MIPS, Sun’s SPARC, MC PowerPC, DEC Alpha memory/memory: e.g. DEC VAX memory/register: e.g. DEC VAX, IBM 360, DEC PDP-11, MC 68000, Intel 80386

11 RISC vs. CISC RISC -- Reduced Instruction Set Computer -- philosophy (instruction sets measured by how well compilers used them) fixed instruction lengths load/store instruction sets all operands of ALU instructions are in registers limited addressing modes limited operations e.g. MIPS, Sun SPARC, HP PA-RISC, PowerPC (AIM), ARM, Renesas Tech. SuperH (by Hitachi), ARM/Thumb, etc. CISC – Complex Instruction Set Computer -- Implies fewer instructions in the set larger register file longer programs good for pipelining simpler control

12 Chapter Summary Instruction Type Instruction Format RISC Design Principles Assembly vs. Machine Language Addressing Modes Classes of Instruction Set Architecture RISC vs. CISC