LAB #2 Xilinix ISE Foundation Tools Schematic Capture “A Tutorial”

Slides:

Advertisements

Similar presentations

Lab7: Introduction to Arduino

Advertisements

08/07/041 CSE-221 Digital Logic Design (DLD) Lecture-8:

1 COMP541 Combinational Logic Montek Singh Jan 16, 2007.

FPGA BASED IMAGE PROCESSING Texas A&M University / Prairie View A&M University Over the past few decades, the improvements from machine language to objected.

16/27/2015 3:38 AM6/27/2015 3:38 AM6/27/2015 3:38 AMTesting and Debugging Testing The process of verifying the software performs to the specifications.

Introduction to Field Programmable Gate Arrays (FPGAs) COE 203 Digital Logic Laboratory Dr. Aiman El-Maleh College of Computer Sciences and Engineering.

ECE 448: Spring 12 Lab 4 – Part 2 Finite State Machines Basys2 FPGA Board.

Introduction to Basys 2. Switches Slide switchesPush button switches.

Introduction to FPGA Design Illustrating the FPGA design process using Quartus II design software and the Cyclone II FPGA Starter Board. Physics 536 –

CPE 169 Digital Design Laboratory Digilent Inc. Nexys Development Board.

Digital Logic Lecture 08 By Amr Al-Awamry. Combinational Logic 1 A combinational circuit consists of an interconnection of logic gates. Combinational.

Chapter 4 Programmable Logic Devices: CPLDs with VHDL Design Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights.

Advanced Digital Circuits ECET 146 Week 3 Professor Iskandar Hack ET 221B,

Experiment #3A: Introduction to Function Reduction, Function Forms, and VHDL Implementation CPE 169 Digital Design Laboratory.

Adders and Multipliers Review. ARITHMETIC CIRCUITS Is a combinational circuit that performs arithmetic operations, e.g. –Addition –Subtraction –Multiplication.

ISE. Tatjana Petrovic 249/982/22 ISE software tools ISE is Xilinx software design tools that concentrate on delivering you the most productivity available.

Lecture #3 Page 1 ECE 4110– Sequential Logic Design Lecture #3 Agenda 1.FPGA's 2.Lab Setup Announcements 1.No Class Monday, Labor Day Holiday 2.HW#2 assigned.

ENG241/ Lab #41 ENG2410 Digital Design LAB #4 Design of Combinational Logic “The Trip Genie”

Boolean Algebra (Continued) ELEC 311 Digital Logic and Circuits Dr. Ron Hayne Images Courtesy of Cengage Learning.

Spring Introduction  Today’s tutorial focuses on introducing you to Xilinx ISE and Modelsim.  These tools are used for Verilog Coding Simulation.

Comments on Lab #4 Annotating Timing Diagrams Draw viewer’s attention to the points you are trying to show / verify –Important output states glitch or.

Advanced Digital Circuits ECET 146 Week 4 Professor Iskandar Hack ET 221G,

1 Introduction to Xilinx ISL8.1i Schematic Capture and VHDL 1.

1 Introduction to Xilinx ISL8.1i & 11.1 Schematic Capture 1.

ENG2410 Digital Design LAB #8 LAB #8 Data Path Design.

ASIC 121: Practical VHDL Digital Design for FPGAs Tutorial 1 September 27, 2006.

ENG2410 Digital Design LAB #6 LAB #6 Sequential Logic Design (Flip Flops)

ENG2410 Digital Design LAB #5 Modular Design and Hierarchy using VHDL.

This material exempt per Department of Commerce license exception TSU Xilinx Tool Flow.

Lecture #3 Page 1 ECE 4110–5110 Digital System Design Lecture #3 Agenda 1.FPGA's 2.Lab Setup Announcements 1.HW#2 assigned Due.

displayCtrlr Specification

CascadedBCDCntr&Display Aim : Capture, simulate and implement a 2-digit, loadable BCD up/down counter, with chip enable I/P (CE) and chip enable O/P (CEO).

Introductory project. Development systems Design Entry –Foundation ISE –Third party tools Mentor Graphics: FPGA Advantage Celoxica: DK Design Suite Design.

ECE 2372 Modern Digital System Design Section 4.8 Xilinx Schematic Capture Simulation Tutorial.

Introduction to ECE 255 Lab Cheng Cheng, Teaching Assistant Department of EECS University of Tennessee.

 Seattle Pacific University EE Logic System DesignAlteraBoard-2 Altera Cyclone II (484 Pin BGA) 22 Pins.

ENG241/ Lab #11 ENG2410 Digital Design LAB #1 Introduction Combinational Logic Design.

1 ENGG 1015 Tutorial Three Examples of Finite State Machines Supplementary notes Learning Objectives  Learn about Design of Finite State Machines Ack.:

11 EENG 1920 Introduction to VHDL. 22 Hardware Description Language A computer language used to design circuits with text-based descriptions of the circuits.

ENG2410 Digital Design LAB #7 LAB #7 Sequential Logic Design “Sequence Recognizer” Using both Schematic Capture and VHDL.

Introduction to Labs Wenchao Cao, Teaching Assistant Department of EECS University of Tennessee.

Teaching Digital Logic courses with Altera Technology

ECE 3450 M. A. Jupina, VU, 2016 Capacitance Sensor Project Goal: Creation of a digital capacitance sensor circuit where a variation in capacitance changes.

Lab Environment and Miniproject Assignment Spring 2009 ECE554 Digital Engineering Laboratory.

Project 1.  Two parts Implement a 3 bit Gray Code Counter Implement a 4-to-1 muxtiplexer  Can be done on Altera (Quartis) or Xilinx 8/22/2012 – ECE.

Building Blocks CS 1308 Computer Literacy and the Internet.

ECE 448 Lab 3 FPGA Design Flow Based on Xilinx ISE and ISim. Using Seven-Segment Displays, Buttons, and Switches.

ACOE161Digital Circuit Design1 Design Of Combinational Logic Circuits.

ECE 448 Lab 3 FPGA Design Flow Based on Xilinx ISE and Isim. Using Seven-Segment Displays, Buttons, and Switches.

Combinational Design, Part 2: Procedure. 2 Topics Positive vs. negative logic Design procedure.

Lecture 1 Gunjeet kaur Dronacharya group of institutions.

LAB #5 Modular Design and Hierarchy using VHDL

Introduction to the FPGA and Labs

EET 1131 Unit 4 Programmable Logic Devices

EGR 2131 Unit 4 Combinational Circuits: Analysis & Design

DE2-115 Control Panel - Part I

LAB #6 Sequential Logic Design (Flip Flops, Shift Registers)

LAB #3 Design of Combinational Logic “The Trip Genie”

LAB #4 Xilinix ISE Foundation Tools VHDL Design Entry “A Tutorial”

Implementing VHDL Modules onto Atlys Demo Board

Lab02 :Logic Gate Fundamentals:

ECE 4110–5110 Digital System Design

LAB #1 Introduction Combinational Logic Design

Programmable Logic Devices: CPLDs and FPGAs with VHDL Design

Logic Gates Practical Objective: to develop an understanding of logic circuits and truth tables.

3.4 Computer systems Boolean logic Lesson 2.

LAB #2 Xilinix ISE Foundation Tools Schematic Capture “A Tutorial”

Founded in Silicon Valley in 1984

Lab 0: Groups and Equipment

Presentation transcript:

LAB #2 Xilinix ISE Foundation Tools Schematic Capture “A Tutorial” ENG2410 Digital Design LAB #2 Xilinix ISE Foundation Tools Schematic Capture “A Tutorial” ENG241/ Lab #2

Lab Objectives Learn the basics of Xilinx ISE tool. Enter your design using Schematic Capture. Implement some simple logic functions on the NEXYS 3 board. Test and Debug your design and verify software simulation and hardware implementation. ENG241/ Lab #2

Xilinx ISE Tool ENG241/ Lab #2

Schematic Capture Sample circuit entered using Schematic Capture. Note that this is not the circuit you will be building ENG241/ Lab #2

Very Important The lab computers employ restore-point software to prevent modification on drive C. This means that if anyone saves their work on Drive “C” IT WILL BE LOST AFTER REBOOTING. The Computers reboot everyday at 4 am automatically. Please save your projects on the “T” Drive and copy it to your “H” drive when you are done working. The “T” drive is common to anyone on that computer, and someone may delete your work accidentally, so always backup your projects on your network “H” drive. Also, to prevent plagiarism of your projects, remove your projects off the “T” drive once they are stored on the network drive. ENG241/ Lab #2

FPGA Power Switch Reset LEDs USB Switches to control input ENG241/ Lab #2

FPGA LUT A B C D Z LUT implementation ENG241/ Lab #2

UCF File It is used to define the Input/Output pin assignment for the FPGA on the NEXYS 3 board. You will use the following assignments in Part 1: NET A LOC = T5; // left most slide switch on NEXYS 3 board NET B LOC = V8 ; // next slide switch on NEXYS 3 board NET C LOC = U8; // third slide switch on NEXYS 3 board NET D LOC = N8; // fourth slide switch on NEXYS 3 board NET E LOC = T11; // left most LED on NEXYS 3 board ENG241/ Lab #2

Digilent Adept Tool The Digilent Adept Tool is used to: Test the FPGA board. Program the FPGA board. Check Appendix A in the Tutorial ENG241/ Lab #2

Behavioral Simulation ENG241/ Lab #2

Test Bench BEGIN A_tb <= '0'; -- apply input combination 00 and check outputs B_tb <= '0'; wait for period; assert ((S_tb = '0') and (C_tb = '0')) report "test failed for input combination 00" severity error; ... … A test for you to check your schematic capture with you’re the truth table that you should have. ENG241/ Lab #2

Part 1 Implement the Following function: Derive its truth table and Circuit diagram. Implement the design using Xilinx ISE Schematic Capture tool Test and Debug your Circuit. Use the UCF file provided to you in the hand-out. ENG241/ Lab #2

Part 2 In this part you will use Xilinx ISE schematic capture tool again to enter your design. The circuit has two inputs (X and Y) and one output (F). The function F is true when X and Y are different, and false when they are the same. Derive the truth table, and give an expression for F. Assume X is MSD Draw the circuit diagram. ENG241/ Lab #2

Cont … Part 2 Enter the design using Schematic Capture. Simulate your design. Go Through the implementation process until you download your design on the NEXYS 3 board. Create the UCF file for this circuit on your own. Verify your Implementation. ENG241/ Lab #2

Academic Misconduct Reports and demos are submitted as a group, but it is a SINGLE group effort You may talk with other groups but sharing codes or reports is NOT ALLOWED Copying reports from previous years is also NOT ALLOWED If we find copying we are REQUIRED to report it