1 Ultrathin Gate Dielectrics on SiGe/SiGeC Heterolayers By Siddheswar Maikap Department of Physics Indian Institute of Technology (IIT), Kharagpur India

2 Who am I ? IIT, Kharagpur, 1950 IIT, Kanpur, 1963 IIT, Bombay, 1958 IIT, Guwahati, 1994 IIT, Delhi, 1961 IIT, Roorkee, 2001 IIT, Madras, 1961

3 Present Supervisor: Professor C. W. Liu, National Taiwan University, Taiwan 11 th February Ph.D Supervisors: Prof. S. K. Ray (Dept. of Physics) and Prof. C. K. Maiti (Dept. of E & ECE), IIT Kharagpur, India July October 2001 Postdoc Supervisors: Prof. Nong. M. Hwang and Prof. Doh. Y. Kim, Dept. of Material Science, Seoul National University, South Korea October December 2002

4 Outline of the Work  Introduction  Growth of group-IV alloy layers  Ultrathin oxides on partially strained layers  Extraction of material parameters for SiGe/SiGeC heterolayers  High-k gate dielectric for alternative SiO 2  Conclusion and Future work

5 Technology Roadmap  Moore’s law: the gate length and cost production lines as a function time. Source: National Technology Roadmap for semicon- ductors, Semiconductor Industry Association, San Jose, USA, 1997 (After D. J. Paul, Adv. Mater., vol. 11, p. 191). Year Channel length (  m) <0.10<0.07 Oxide thickness (nm) <4

6 Requirements of gate quality ultrathin oxide  High quality Si/SiO 2 interface  Low defect density  Stability under hot carrier stress  Low thermal budget  Good barrier properties against impurity diffusion  Reduced B-penetration from doped poly-Si gate

7  Band-gap engineered semiconductor devices for VLSI/ULSI technology  Enhancement of low field hole mobility: CMOS devices  Heterojunction bipolar transistor (HBT) for high speed digital and microwave circuits  Modulation doped field effect transistor (MODFET)  Quantum well detectors  Resonant tunneling diodes Why SiGe?

8 Growth of Group-IV Alloy Layers on Si Schematic diagram of strained and relaxed epilayer on a Si substrate. In the relaxed layer, many dislocations are seen at the epi/substrate interface. According to Vegard’s rule: where, a Si =5.43 Å, a Ge =5.65 Å and a c =3.57 Å

9 Critical Layer Thickness Critical layer thickness of Si 1-x Ge x films as a function of Ge mole fraction. Lines show theoretical kinetic model for various growth temperature. Figure is after D. C. Houghton et al., J. Appl. Phys., vol. 70, 1991, p

10 Role of C in SiGe System   Strain compensation by substitutional C in SiGe: 1 at % C compensates at % Ge   Possibility of SiGeC system with either compr- essive or tensile strain: Additional flexibility in strain & band-gap engineering  Better surface smoothness  Higher critical layer thickness  Higher strain relaxation temperature According to Vegard’s rule: where, a Si =5.43 Å, a Ge =5.65 Å and a c =3.57 Å

11 Strain Compensation Critical layer thickness of Si 1-x-y Ge x C y as a function of Ge and C concentration. Figure is after Amour et al., Thin Solid Film., vol. 294, 1997, p. 112.

12 High Resolution X-ray Diffraction (004) HRXRD spectra from Si 0.8 Ge 0.2 and Si 0.69 Ge 0.3 C 0.01 films According to Vegard’s rule: where, a Si =5.43 Å, a Ge =5.65 Å and a c =3.57 Å

13 Atomic Force Microscopy AFM (5  m x 5  m) scan of film surface. (a) Si 0.6 Ge 0.4 sample (~22 Å rms), (b) Si 0.56 Ge 0.4 C 0.04 sample (~1.3 Å rms). SampleZ rms ( Å ) Si 0.6 Ge Si 0.56 Ge 0.4 C Si 0.74 Ge Si 0.69 Ge 0.3 C

14 Gate oxides on group-IV alloy layers  Problem in conventional thermal oxidation:   High temperature oxidation: Not suitable for  group-IV alloys due to strain relaxation  Selective oxidation of Si: Ge segregation and C precipitation  Misfit dislocations due to high temperature process  Degradation of mobility due to relaxed layer at processing temperature  Solution:   Low temperature oxidation  Minimize the misfit dislocation

15 Low Thermal Budget Methods for Oxidation Why Microwave Plasma Oxidation  Rapid thermal oxidation (RTO)  Low pressure chemical vapor deposition (LPCVD)  Plasma oxidation    Electrodeless, Low self bias and High ionization efficiency  Low temperature (<200 o C) growth   Reduced impurity distribution   Absence of Ge segregation   Absence of C precipitation

16 Experimental Setup Schematic diagram of microwave discharge cavity system  Oxidation time: 2 min  Initial Pressure: Torr  Growth Pressure: 1.0 Torr  Temperature: ~200 o C  Growth rate: 40  5 Å/min  Refractive index: (Ellipsometry)

17 High Resolution X-ray Diffraction High resolution X-ray diffraction characteristics for (a) as-grown, (b) plasma grown and (C) thermal (750 o C, 100 min) oxides on Si Ge 0.3 C samples.

18 Location of Different Trap Charges Location of trapped charges at different regions in the MOS structures.

19 Fixed Oxide Charge and Interface State Density where, A is the gate area,  ms is the work function between metal and semiconductor, G max is the maximum conductance,  is the angular frequency, and C m is the capacitance at G max. C-V and G-V characteristics for plasma grown Si 0.69 Ge 0.3 C 0.01 sample. Q f /q= -2.7x10 11 cm -2 D it = 5.4x10 11 cm -2 eV -1

20 Extraction of Material Parameters of SiGe/SiGeC Heterolayers  Hole confinement characteristics  Extraction of Si-cap layer thickness  Extraction of buried and surface channel threshold voltages  Determination of valence band offset: Si 1-x Ge x and Si 1-x-y Ge x C y heterolayers  Generation lifetime of group-IV alloy layers

21 Hole confinement characteristics High frequency (1 MHz) C-V characteristics of a MOS capacitor. Simulated HF and low frequency C-V characteristics are also shown.

22 Extraction of Si-cap Layer Thickness Apparent doping concentration vs. distance from the Si/SiO 2 interface. Unconsumed Si-cap layer thickness: 30A

23 Extraction of Threshold Voltages Experimental apparent doping vs. gate voltage characteristics. 1-D numerical simulation of hole charge in buried channel (Q H, SiGe) and in surface channel (Q s, Si-cap) as a function of gate voltage.

24 Effect of Ge Concentration SiGe-well Si-cap Low frequency C-V characteristics Hole concentration in Si-cap and SiGe-well

25 Extraction of Valence Band Offset (  E v ) where, and where  H Potential at top heterointerface  F Fermi potential  TH Potential at threshold at the top heterointerface t cap Thickness of Si cap layer  Si Permittivity of Si X dm Maximum depletion layer width  V T =V TH -V TS, gate voltage window

26 Valence Band Offset: SiGe and SiGeC Summary of experimentally measured  E v in strained Si 1-x Ge x and partially strain compensated Si 1-x-y Ge x C y heterolayers.

27 Generation Lifetime in Si-based Heterolayers SampleDoping (cm -3 )  g (  s) CZ Si (Schwartz et al.) 5x Control Si (this work)5x Si 0.82 Ge 0.18 (Schwartz et al.)3x Si 0.9 Ge 0.1 (Riley et al.)2.5x Si 0.8 Ge 0.2 (this work)2x Si 0.8 Ge 0.18 C 0.02 (Lippert et al.) 5x Si Ge 0.2 C (this work)2x Transient response of capacitance-time plot for a partially strained Si Ge 0.2 C MOS capacitor.

28 Why high-k dielectric ? High leakage current Low breakdown field Poor reliability Problem in conventional ultrathin SiO 2 ( <2 nm): Solution: High-k dielectric as a gate material

29 Why ZrO 2 and HfO 2 ?  High dielectric (  ) constant:  Thermodynamically stable on Si  High breakdown field: ~ MV/cm  Large band gap: 5 -8 eV  Low leakage current J. Robertson, MRS Bull. March 217 (2002)

30 Deposition conditions of ZrO 2 films on SiGe/SiGeC by RF magnetron sputtering  Substrate temperature: 350 o C  Base pressure: 5x10 -6 Torr  Deposition pressure: 0.2 Torr  Ar:O 2 : 4:1  Deposition time: 20 min  RMS roughness: ~ 6.5 nm for 1hr ~ 8.0 nm for 1.5 hr SiGe VgVg Al ZrO 2 /HfO 2 Interfacial layer

31 C ox = 1116 pF Glue ZrO 2 ~ 8.5 nm IL ~ 3.9 nm Si 0.69 Ge 0.3 C 0.01 ~ 40 nm Si epilayer

32

33 ZrO 2 with interfacial lay er Interfacial lay er 1/C eq = 1/C ZrO2 + 1/C interfacial layer t eq = (3.9/k IL )t IL + (3.9/k high-k )t high-k ZrO 2 (k) ~ 17.5 IL (k) ~ 7.0 Effective k ~ 12.2 EOT ~ 3.9 nm

34 Ultra-thin HfO 2 films on p-Si (a)(b)(c) HfSiO HfO Hf NN

35 H-related trap  Substrate temperature: 350 o C  Base pressure: 5x10 -6 Torr  Deposition pressure: 13.5 mTorr  Ar/N 2 : 19 sccm: 7 sccm  Deposition time: 3 min

36 Conclusion  High quality strained Si 1-x Ge x and partially strain compensated Si 1-x-y Ge x C y heterolayers: UHVCVD  Strained layer characterization:  Composition and thickness of group-IV alloy layers: SIMS analysis  Crystalline quality: HRXRD study  Surface roughness: AFM study  Low-temperature plasma oxidation: Preserve the strain in group-IV alloy layers

37  Extraction of material parameters for SiGe and SiGeC heterolayers: Threshold voltages of buried and surface channel, valence band offset, and carrier generation lifetime  ZrO 2 and HfO 2 high-k gate dielectrics Physical characterization: HRTEM, ToF-SIMS, XPS and AES measurements Electrical characterization: C-V, G-V, I-V and gate voltage shift

38 Future scope  Annealing effect on ZrO 2 and HfO 2 high-k dielectrics on Si, SiGe, SiGeC and strained-Si heterolayers  Stacked gate dielectrics, NH 3 /HfO 2 /N 2 O, on Si, SiGe, SiGeC and strained-Si heterolayers

39 Acknowledgments:  The author is grateful to Professor S. K. Banerjee, The University of Texas at Austin, for providing experimental support for the growth of strained Si 1-x Ge x and Si 1-x-y Ge x C y samples used in this study.  The author gratefully acknowledge financial support from the Creative Research Initiatives Program of the Korea Ministry of Science and Technology, South Korea