SI Fundamentals Short Course - Equalization Howard Heck Intel Corporation

Contents Introduction Channel Characteristics Continuous Time Linear Equalizers Discrete Time Linear Equalizers Decision Feedback Equalizers Adaptive Equalization Crosstalk Cancellation Summary

We use equalization to improve timing margins. Motivation Signaling speeds continue to increase while interconnects change incrementally. 4-Layers boards with FR4 still rule. Solution spaces cannot shrink indefinitely. Board and silicon timings must continue to scale together. For example: The spec for PCIe Gen1 allocates 65 ps to the channel (1/3 of 2.5 GT/s timing budget). Without scaling, interconnects will take 2/3 of the Gen2 5 GT/s timing budget. We use equalization to improve timing margins.

Introduction Systems with equalization are best viewed as communications links where each block filters the signal. The signal at the receiver input is: binary 1 binary 0 where ht(t) = transmitter filter hc(t) = channel impulse response n(t) = noise r(t) = received signal * = convolution operation

Introduction #2 Let’s simplify things slightly by looking at the transmitter, interconnect channel, and receiver. The signal at the input to the receiver is a function of the transmitted signal and the channel insertion loss: time domain frequency domain  We describe the channel as a band limited filter:

Ideal Channel S21(f) is constant: zero amplitude distortion qS21(f) is a linear function of frequency: constant delay at all frequencies  zero phase distortion Result: distortionless transmission, open data “eye.”

Real Channel S21(f) isn’t constant: Losses increase with frequency qS21(f) isn’t linear with frequency: er varies with frequency Result: Amplitude and phase distortion cause “smearing” of pulses (ISI) which closes the “eye” diagram.

The Ideal Equalizer With an equalizer in the channel: The ideal response requires an equalizer that responds as the inverse of the channel: Equalized The ideal response is typically not practical. Cost & power constrains the design. Goal: reduce distortion to tolerable levels. [dB] Loss Interconnect Channel f [GHz]

Overview of Techniques The equalizer may be placed anywhere in the channel. Often done at the transmitter (Tx), receiver (Rx), or both. Interconnects can contain equalizing filters, too. Popular types: Continuous time filters (with/without amplification). Discrete linear equalizers (Tx pre-emphasis or Rx). Decision feedback equalizers (DFE). Other types of filtering can compensate for other sources of distortion (e.g. crosstalk cancellers). We’ll look at each.

Passive Continuous Linear Equalizer The passive CLE is a high pass filter. Low frequency components are attenuated. Amplification of high frequency components is possible, too. The filter can be made of discrete components, integrated into the silicon, or even built into cables or connectors.

Passive Continuous Linear Equalizer CTLE Closed eye -21.0 dB -16.0 dB PCB Closed eye PCB+CTLE The passive equalizer doubles the usable spectrum.

Passive CTLE @10 Gb/s Non-Equalized Equalized Eye mask : 20 mV x 50 ps

Transmit Equalization (a.k.a. Pre-Emphasis) Isolated bits or rapidly alternating 0s/1s don’t build up to the full swing at the receiver in a lossy channel. This gives a closed eye at the receiver. Non-Equalized Pre-emphasis adjusts the magnitude of the transmitter output based on prior bit values. Often done by attenuating successive bits (“de-emphasis”). This reduces the maximum swing, but produces an open eye. Equalized

Pre-Emphasis Circuit DLEs use finite impulse response (FIR) filters. The input stream propagates thru a series of delay lines. Each line typically has a delay of one unit interval. The input signal is sampled between each delay line and multiplied by a weighting factor (Ck). Negative subscripts compensate “precursor” ISI, positive for “postcursor” ISI. D C -1 1 2 S y k x The outputs from the weights are summed to produce the transmitter output. The number of taps depends on the length of the channel relative to the unit interval of the data.

Tx Pre-emphasis Example Pulse arrives filter input & is multiplied by C-1, generating a precursor pulse of -50 mV amplitude and 1 ns duration. 2 After 1 ns delay, pulse appears at tap 2 & is multiplied by C0, generating the 400 mV, 1 ns cursor pulse. 400 mV 600 mV 1 ns 1 - 50 mV 3 4 x T T T k C C C C - 1 1 2 4 50 mV 3 - 100 mV S y k 1 ns later, the pulse is at tap 3 tap & gets weighted with C1, generating the first postcursor pulse (-100 mV amplitude, 1 ns duration). 1 ns later, the reaches the final tap, is multiplied by C2, creating the +50 mV, 1 ns 2nd postcursor pulse.

Tx Pre-emphasis Pulse arrives filter input & is multiplied by C-1, generating a precursor pulse of -50 mV amplitude and 1 ns duration. After 1 ns delay, pulse appears at tap 2 & is multiplied by C0, generating the 400 mV, 1 ns cursor pulse. 1 ns later, the pulse is at tap 3 tap & gets weighted with C1, generating the first postcursor pulse (-100 mV amplitude, 1 ns duration). 1 ns later, the reaches the final tap, is multiplied by C2, creating the +50 mV, 1 ns 2nd postcursor pulse.

FIR Filter Response Time Domain Frequency Domain where ck=tap Coefficient, k=tap number (0=cursor), N=# of taps N=2 C0=.75 C1=-0.2 C2=-0.05 -7 -6 -5 -4 -3 -2 -1 2 4 6 8 10 f [GHz] |H(f)| [dB] 6.4 Gb/s 10 Gb/s 12.8 Gb/s To derive the frequency domain transfer function apply the time shift property of the Fourier transform, w(t-T) ↔ W(f )e- j2pfT, to the time domain filter response w/ T = unit interval.

Rx Discrete Time Linear Equalizer (DLE) The receive-side DLE works just like the transmitter pre-emphasis circuit. The only difference is that it samples the incoming analog voltage. Uses a “sample & hold” circuit at the input, which provides the input signal stream to the FIR. C -1 1 2 D S y k x

Discrete Linear Equalizer Design Conceptually, we want the receiving equalizer to generate a set of canceling “echoes” -2 -1 1 2 3 4 5 time (UI) -3 -0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 0.08 0.10 voltage (V) Equalized Received Desired Equalizer Since we sample at predetermined points, the equalizer design can be straightforward, but will only cancel ISI at the sample points. Tap weights are selected to subtract ISI effects from adjacent bits.

DLE Design #2 Equalizer 2N+1 taps, weights C-N, C-N+1,…, CN, Output samples {yn} are found by convolving the input samples {xn} and the tap weights {Cn}:

DLE Design #3 In matrix form: where Input matrix columns represent the taps of the equalizer, rows represent consecutive time steps with an interval between steps that is equal to the tap spacing of the equalizer. x is square with npre + npost + 1 rows and columns. It shows the propagation of the input samples through the equalizing filter. y is the vector of consecutive output samples. c vector is the vector of equalizer tap coefficients.

DLE Design #4 If x is square, then # rows = # columns = # elements in c. Then: We can set the desired output values, y = ytarg, and use the input samples, x, to set c. This is known as the zero forcing solution (ZFS).

ZFS Equalizer DLE Design Steps: Dispose of the top N and bottom N rows of x. This transforms it into a square matrix with dimension 2N +1 by 2N+1, in order to operate with the y vector, which has dimension 2N+1. Set equalized output vector, ytarg, to be equal to zero at N sample points on either side of the desired pulse.

Example: Zero Forcing Solution Determine cn for a 3 tap equalizer (N=2) from the pulse response (i.e. a training pulse) using the zero forcing solution. Given: Zero forcing: Then: Carrying out the matrix multiplication and solving the simultaneous equations, or using , get: c-1 = -0.214, c0 = 0.963, c1 = 0.345

Linear Equalizer Limitations The linear equalizer can’t distinguish between the signal and noise. HF noise is amplified. Data rate is limited by SNR according. Noise becomes a primary design consideration. An alternative to a linear equalizer is a decision feedback equalizer (DFE). Other methods for setting tap weights may provide better results. f [GHz] Loss [dB] Channel Equalized Channel Linear Equalizer Noise Enhanced Noise

Decision Feedback Equalizers Bit slicer h(t) S r(t) Channel n(t) t=0 yk xk FBF Characteristics: No noise enhancement Input to FBF has no noise, as opposed to DLE input. Assumes all past decisions are correct Erroneous decisions corrupt future decisions. There are coding methods to minimize impact. Corrects for only post-cursor ISI

DFE Operation The DFE uses the same FIR filter structure as the DLE. Feedback Filter The DFE uses the same FIR filter structure as the DLE. The input signal is summed with the feedback signal to provide input to a bit slicer, which decodes the signal into either a “1” or a “0”. The output from the bit slicer is used as input to the FIR filter.

DFE Operation No EQ DLE DLE + DFE 89 ps DLE 90 mV 96 mV 76 ps DLE + DFE The DFE requires an open eye, so it is typically used with a linear equalizer on the front end.

Adaptive Equalization Adaptive DFE Ideally, tap coefficients are tuned to each system to account for operational (V, T) and manufacturing variation. This is done using adaptive algorithms. Perfect adaptation isn’t practical. Limited by things like update rate, coefficient resolution, etc. Adaptive DLE

Crosstalk Cancellation Some noise sources can be compensated (some can’t). A simple way to cancel the effects of crosstalk is shown below (Zerbe 2001). Operation: XTC samples outgoing data is & multiplies it with a tap weight over a unit interval. The weighted signal is sent to the adjacent signal on each side, where it is summed with the outgoing data.

Summary Channels act as filters that cause both amplitude and phase distortion of signals. Transmitters and receivers can be designed as filters to compensate for non-ideal channel behavior. Discrete linear equalizers at the transmitter and receiver are seeing wide use for multi-Gb/s signaling. Multiple techniques are available for setting filter tap weights. Crosstalk can be cancelled, too.

References S. Hall and H. Heck, Advanced Signal Integrity for High Speed Digital Designs, John Wiley & Sons, to be published in 2009. Couch, Leon, Digital and Analog Communication Systems, 2nd edition, MacMillan, New York, 1987. W.J. Dally, J. Poulton, “Transmitter Equalization for 4-Gbps Signaling,” IEEE Micro, January/February 1997, pp. 48-56. Jaussi, James, et. al., “8-Gb/s Source-Synchronous I/O Links With Adaptive Receiver Equalization, Offset Cancellation, and Clock De-Skew,” IEEE Journal of Solid-State Circuits, Vol. 40, No. 1, January 2005, pp. 80-88. Sun, Ruifeng, Park, Jaejin, O’Mahony, Frank, and C. Patrick Yue, “A Low-Power, 20-Gb/s Continuous-Time Adaptive Passive Equalizer,” IEEE Symposium on Circuits and Systems (ICAS) 2005, May 23-26, 2005, pp. 920-923. Liu, Jin, and Xiaofen Ling, “Equalization in High-Speed Communication Systems,” IEEE Circuits and Systems Magazine, Vol. 4, No. 2, 2004, pp. 4-17. Lucky, Robert, “The Adaptive Equalizer,” IEEE Signal Processing Magazine, May 2006, pp. 104-107. Qureshi, Shahid, “Adaptive Equalization,” Proceedings of the IEEE, Vol. 73, No. 9, September 1985, pp. 1349-1387.