EEE515J1_L5-1/8 EEE515J1 ASICs and DIGITAL DESIGN Designing FSMs Ian McCrumRoom 5D03B Tel: voice mail on 6 th ring Web site:

EEE515J1_L5-2/8 Example 2A A FSM with Inputs: Polaris Missile Launcher (D-types, straight binary, Output decoder) Assume 2 officers must supply an input to a system to launch the missile, any false code causes an abort. PENDING YELLOW ALERT ORANGE ALERT RED ALERT 0X/0, 10/0 11/0 11/1 0X/0, 10/0 There is a flaw/bug/feature in this design. A common problem in FSMs is to specify EXACTLY when the output is to occur, in time A sequence of 11,11,11 (Missile launches at the instant of ENTERING red alert, should be on exit!)

EEE515J1_L5-3/8 PRES STATE (state bits= ZY) I/ps AB Next ST DETAIL FOR BIT Z DETAIL FOR BIT Y OUTPUT 1P00 P 00RESET0 00 2P0001P 00RESET0 00 3P0010P 00RESET0 00 4P0011Q 01RESET0SET10 5Q0100P 00RESET0 00 6Q01 P 00RESET0 00 7Q0110P 00RESET0 00 8Q0111R 10SET1RESET00 9R1000P 00RESET R 01P 00RESET R10 P 00RESET R1011S 11SET S1100P 00RESET S1101P 00RESET S1110P 00RESET S11 S 11SET1 11 The equations to make this machine will require detecting 4 different on- terms /Z/YAB /ZYAB Z/YAB ZYAB We also need two three input or gates… Cost = 34p

EEE515J1_L5-4/8 Pulse Generators : The generic family consider carefully the detailed timing of i/p and o/p, Is the input to “trigger” when the input is high, or when a low to high transition occurs on the input; level triggered or edge triggered. What polarity is required (though I will only cover low-high or high triggers here) Exactly when is the output to go high? Normally at the first active clock transition after the input trigger condition is met. an example follows of a circuit which responds to a low to high transition and generates one pulse. The input is allowed to stay high but only one pulse is ever generated. Only when the input goes low is it again “armed”, thus it is truly edge triggered and is not “re-triggerable”. We assume the input can only change infrequently and that the clock is much faster than the period of input changes. CLOCK

EEE515J1_L5-5/8 The development of the state diagrams evolves from the sequences above. Ensure you can follow what each does. The last diagram is best, though even this assumes the input does not go low and then high again before the pulse completes its output A detailed timing diagram is better at representing exactly what is desired. TUT QUESTION:L5(a) develop circuits to o/p 3 pulses TUT QUESTION:L5(b) develop circuits to o/p 5 pulses Clk-to-Q propagation delay INPUT OUTPUT CLOCK

EEE515J1_L5-6/8 Quick ways of designing machines: The one-Hot method to design any finite state machine (FSM) using the one-hot method you use one D-type flip-flop per state, you must use D-types for the method to work. You must also use the special state code , , etc, I.e n-1 zeroes and a single ‘1’, (called the “HOT” state!) Variations do exist, ONE-HOTZ and TWO-HOT for instance, but we will only deal with one-hot here. The secret to the method is to look carefully at the state diagram, for each state you will write down a term for every arrowhead entering that state.

EEE515J1_L5-7/8 e.g Pulse Generator using one-hot Input I A B C O/P Clock A.d = A * /I + C * /I;Cost = =12 B.d = A * I;Cost = 6+2 =8 C.d = C * I + B;Cost = 6+2+2=10 O/p = B; A/0B/1 C/0 0 1 X 1 0

EEE515J1_L5-8/8 Summary Week 4 You can… design counters that count up (no inputs) You can… design counters that can hold or count You can… design counters that can count up/down or reset You can… design counters with D-type flipflops You can… design counters with JK-type flipflops You can… design using a state assignment related to the desired outputs You can… design pulse generators You can… design using a straight binary state assignment You can… design using a one-hot state assignment You can… cascade counters synchronously You can… appreciate why synchronous counters are better than asynchronous counters You can use Quartus to design multiple sheet designs that use BUSes and develop your own library parts Next comes … VHDL