Annual Meeting – October 8, Status of the CEA Saclay R&D activities on pixelised readout of TPC David Attié, Paul Colas, Marc Riallot, Franck Senée Eudet Annual Meeting, Ecole Polytechnique 8-10 October 2007

Annual Meeting – October 8, Overview TimePix wafer tests Status of TimePix/Micromegas chamber at Saclay Large Prototype Endplate Next steps

Annual Meeting – October 8, TimePix wafer tests at CERN 20 wafers from the first run have been tested  ~ 66 % of chips are usable 1 m² ~ 4400 chips ~ 68 wafers Thanks to X. LLOPART (CERN)

Annual Meeting – October 8, TimePix/Micromegas chamber at Saclay Field cage Cover Micromegas mesh Medipix2/TimePix chip M. RIALLOT (DAPNIA/SEDI) Windows for X sources Windows for  source Blueprint :

Annual Meeting – October 8, TimePix/Micromegas chamber at Saclay 3 Specific Micromegas meshes build at CERN are available -55  m of pitch holes -75  m of pillar diameter -50  m of gap

Annual Meeting – October 8, TimePix/Micromegas chamber at Saclay

Annual Meeting – October 8, TimePix/Micromegas chamber: status The field cage is ready to work in He/Iso 80/20 (the cathode bear up to 6 kV) and Ar/Iso mixture 1 TimePix dead by HV accident 2 TimePix Chip don’t show the same behavior after putting up the micromegas mesh 4 TimePix have been protected by 20  m of amorphous silicon  cosmic tracks should be observed soon !

Annual Meeting – October 8, Large Prototype endplate Interchangeable Micromegas bulk technology  = 80cm D. Peterson, Cornell

Annual Meeting – October 8, Micromegas Large Prototype endplate Pad ~ 2,8 x 6, 8 mm² HT connection

Annual Meeting – October 8, Deliverable panel with TimePix 1x8 chips Si-Prot+Ingrid 1 MUROS Pad ~ 2,8 x 6, 8 mm² HT connection

Annual Meeting – October 8, Deliverable panel with TimePix 2x8 chips Si-Prot+Ingrid 2 MUROS Pad ~ 2,8 x 6, 8 mm² HT connection

Annual Meeting – October 8, Large Prototype Endplate

Annual Meeting – October 8, Next steps 4 Si-protected TimpePix are ready to be tested with the TimePix chamber The design engineering about a PCB board of 1x8 TimePix matrix has started Add “Integrated Grid” (InGrid) on top a matrix (2x4, 1x8,…) Helpful to have one panel-box for tests before LP endplate