Characterization presentation Winter 2009-10 Performed by: Tomer Michaeli 052792769 Liav Cohen 301242509 Supervisor: Shlomo Beer Gingold In collaboration.

Slides:



Advertisements
Similar presentations
Yaron Doweck Yael Einziger Supervisor: Mike Sumszyk Spring 2011 Semester Project.
Advertisements

System Block Diagram VCO As A Multiple Signal Oscillator 4 to 1 Power Combiner System Layout System Practical Operation – room 319 “To do” List Gantt.
CSICS 2013 Monterey, California A DC-100 GHz Bandwidth and 20.5 dB Gain Limiting Amplifier in 0.25μm InP DHBT Technology Saeid Daneshgar, Prof. Mark Rodwell.
Chapter 3 Basic Logic Gates 1.
CHAPTER 1 Digital Concepts
Software-defined Radio using Xilinx (SoRaX) By: Anton Rodriguez & Mike Mensinger Advised by: Dr. In Soo Ahn & Dr. Yufeng Lu.
1 DIFFERENTIAL POLARIZATION DELAY LINE Controller FINAL REPORT D0215 Supervisor : Mony Orbach Performed by: Maria Terushkin Guy Ovadia Technion – Israel.
Students: Nir Engelberg Ezequiel Hadid Supervisor: Mony Orbach In association with: November 23, Winter 2004.
Page 1 Simplifying MSO-based debug of designs with Xilinx FPGAs.
Students: Nir Engelberg Ezequiel Hadid Supervisor: Mony Orbach In association with: September 28, Winter 2005.
Characterization Presentation Spring 2006 Implementation of generic interface To electronic components via USB2 Connection Supervisor Daniel Alkalay System.
IRAM Test Board James Beck ( )
Firmware implementation of Integer Array Sorter Characterization presentation Dec, 2010 Elad Barzilay Uri Natanzon Supervisor: Moshe Porian.
Performed by: Uri Niv Hadas Preminger Instructor: Mony Orbach Cooperated with: Physics Dep. המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory.
University College Cork IRELAND Hardware Concepts An understanding of computer hardware is a vital prerequisite for the study of operating systems.
EEG Machine By The All-American Boys Featuring Slo- Mo Motaz Alturayef Shawn Arni Adam Bierman Jon Ohman.
Electronics II Lab. Two Weeks. power connections Solderless Prototyping Board jacks for power connections.
Students: Asulin Ofir Heller Itai Supervisor: Mony Orbach In association with: June 16, summer 2006.
Performed by:Roi Sherman Eyal Wilamowski Instructor: Mr. Michael Itzkovich המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון.
USB Adapter for Experiment Board Created By : Itai Heller Ofir Asulin Supervised By: Mony Orbach.
Presenting: Yaron Yagoda Kobi Cohen DSP SWITCH Digital Systems Laboratory Winter Supervisor: Isaschar Walter Mid-Term Presentation.
USB Adapter for Experiment Board Created By : Itai Heller Ofir Asulin Supervised By: Mony Orbach.
Intelligent Phone Service Selector Senior Design Project 2006 Advisor: Sandip Kundu Members: Adam Conway Anh Bao Nguyen (manager) Areej Pirzada Dan Verdolino.
ILAB (iTASK Module) Preliminary Design Review EE 496 March 3, 2007 Archimedes.
Students: Nir Engelberg Ezequiel Hadid Supervisor: Mony Orbach In association with: January 3, Winter 2005.
Robotic Arm Controller A VLSI Implementation Team: Justin Hamann & Dave McNamara Team: Justin Hamann & Dave McNamara Advisor: Dr. Vinod Prasad Advisor:
Implementation of DSP Algorithm on SoC. Characterization presentation Student : Einat Tevel Supervisor : Isaschar Walter Accompany engineer : Emilia Burlak.
1 Mid-term Presentation Implementation of generic interface To electronic components via USB2 Connection Supervisor Daniel Alkalay System architectures.
Performed by: Nir Engelberg & Ezequiel Hadid Instructor: Mony Orbach Cooperated with: Electrical Engineering Laboratory המעבדה למערכות ספרתיות מהירות High.
P07301 Summary Data Acquisition Module. Team Members.
Memory Sephiroth Kwon GRMA
General Purpose FIFO on Virtex-6 FPGA ML605 board midterm presentation
FDR Presentation Personal Health Monitoring Device Bassam Noaman Dina El-Eissa Mentor: Prof Zhenyu Guo Instructor: Prof J Silverman 4/12/00.
Students: Oleg Korenev Eugene Reznik Supervisor: Rolf Hilgendorf
General Purpose FIFO on Virtex-6 FPGA ML605 board Students: Oleg Korenev Eugene Reznik Supervisor: Rolf Hilgendorf 1 Semester: spring 2012.
Special Topic-I PLL Basics and Design By, Anil Kumar Ram Rakhyani (akram)
Technion – Israel Institute of Technology Department of Electrical Engineering Winter 2009 Instructor Amit Berman Students Evgeny Hahamovich Yaakov Aharon.
Phase-Locked Loop Design S emiconducto r S imulation L aboratory Phase-locked loops: Building blocks in receivers and other communication electronics Main.
9 MSI Logic Circuits Some of digital system operations: Decoding and encoding; multiplexing; demultiplexing; comparison; code converting; data busing.
By: Oleg Schtofenmaher Maxim Fudim Supervisor: Walter Isaschar Characterization presentation for project Winter 2007 ( Part A)
Matrix Multiplication on FPGA Final presentation One semester – winter 2014/15 By : Dana Abergel and Alex Fonariov Supervisor : Mony Orbach High Speed.
Alex Apel Stephen Rashid Justin Robinson. Overview System Architecture PC Software Design Block Diagram GUI Design Digital Hardware Design Description.
Jitter Experiment Final presentation Performed by Greenberg Oleg Hahamovich Evgeny Spring 2008 Supervised by Mony Orbah.
Characterization Presentation Characterization Presentation OFDM implementation and performance test Performed by: Tomer Ben Oz Ariel Shleifer Guided by:
Final Presentation Final Presentation OFDM implementation and performance test Performed by: Tomer Ben Oz Ariel Shleifer Guided by: Mony Orbach Duration:
Multiplexers and Demultiplexers
Technion - Israel institute of technology department of Electrical Engineering High speed digital systems laboratory 40Gbit Signal Generator for Ethernet.
Wireless communication Emmanuel Gyebison. Transmission Signals must be converted into digital values, using a circuit called ADC (Analog to Digital Converter),
ADVANCED DIGITAL DESIGN DESIGN EXERCISE I Metastability Measurement and Analysis.
Final Presentation Winter 2010 Performed by: Tomer Michaeli Liav Cohen Supervisor: Shlomo Beer Gingold In collaboration with: characterization.
Wisdom stone Development of smart detectors system – generation B Final Presentation Presented by: Emanuel Dima, Elad Kadosh Supervisor: Boaz Mizrachi.
DDRIII BASED GENERAL PURPOSE FIFO ON VIRTEX-6 FPGA ML605 BOARD PART B PRESENTATION STUDENTS: OLEG KORENEV EUGENE REZNIK SUPERVISOR: ROLF HILGENDORF 1 Semester:
PowerBench Programmable Power Supply Dror Lazar Moran Fishman Supervisor: Boaz Mizrahi Winter Semester 2009/10 HS DSL.
1 Dual-V cc SRAM Class presentation for Advanced VLSIPresenter:A.Sammak Adopted from: M. Khellah,A 4.2GHz 0.3mm 2 256kb Dual-V CC SRAM Building Block in.
Lab Environment and Miniproject Assignment Spring 2009 ECE554 Digital Engineering Laboratory.
ECE 554 Miniproject Spring
ADVANCED DIGITAL DESIGN DESIGN EXERCISE I Metastability Measurement and Analysis.
1 Direct Digital Synthesizer STUDENT : Tsung-Han Tu SN : M
Performed by: Tomer Michaeli Liav Cohen Instructor: Shlomo Beer Gingold Cooperated with: המעבדה למערכות ספרתיות מהירות High speed digital.
Computer Maintenance Unit Subtitle: CPU’s Trade & Industrial Education
Electronics for Physicists
. - t !!l t. - 1f1f J - /\/\ - ' I __.
Clock Domain Crossing Keon Amini.
Yusri Maslamani Mohammad Essa Bleal Azaar Supervisor : Dr. Falah Hasan
Team 2 Yimin Xiao Jintao Zhang Bo Yuan Yang Yang
.. '.. ' 'i.., \. J'.....,....., ,., ,,.. '"'". ' · · f.. -··-·· '.,.. \...,., '.··.. ! f.f.
ECE 477 Final Presentation Team 2 Spring 2012
Experiments in Digital & Analog Wireless
500 nm WRITE VOLTAGE 0 V.
TCAD Simulation and test setup For CMOS Pixel Sensor based on a 0
Presentation transcript:

Characterization presentation Winter Performed by: Tomer Michaeli Liav Cohen Supervisor: Shlomo Beer Gingold In collaboration with: characterization of synchronizers and metastability and metastability

Motivation In modern systems, there are several domains with different frequencies. To communicate between them synchronization is needed. Synchronization is achieved by means of a synchronizer’. Designing and building synchronizers is one of the main priorities of the most leading companies in the world because efficient synchronization system will enable significant power saving.

Project subject Manual measurements of synchronization Circuits and comparison to results on chip. Use the word direct instead of Manual Direct measurments

Project goals Learn the direct measurement method. Building and improving of a measurement system for synchronization to characterize performance of synchronizers.

Blocks Diagram f1 f2 FF scope FF scope f1 f2 FPGA Extra generator M.B --Test chip

Required equipment An oscilloscope that can create histograms FPGA board DLP daughter board. Signal generator Voltage regulator Test chip board PC, including Xillinx ISE, Visual Studio.

Test Environment Test Chip 65nm FPGA board Signal generator DLP socket (PC) MUX socket The test environment is composed by the FPGA board that generates control and data signals for the 65nm Synchronizer test chip.

Project Schedule DurationTask 7 weeksLearn the subject and build the measurement system 4 weeksGet the results and compare to the results from the chip 3 weeksAnalize the results