L28:Lower Power Algorithm for Multimedia Systems(2) 성균관대학교 조 준 동

Low Power Video Processor Uzi Zangi, Technion - VLSI Systems Research Center, 1997 Asynchronous logic to save power ý Didn’t work because:Slow design (13.5MHz) &Small circuit (<100K gates) : clock load is small.Adding Async. control costs more then clocking. Gated clock ý Didn’t work because: 6 Frequency is very low (13.5MHz). 6 Register activity is very high. 6 No need for clock tree.

Minimizing bus switching ý Transfer the value or it’s negative on the bus, according to the minimum number of toggle bits. ý Add one bit that will indicate the polarity of the bus. ý Good for buses with: 4 large number of bits (more than 10). 4 High capacitance (more then 2pF). 4 High toggle activity (more then 1/2). ý Overheads: 8 Routing of one more bit. 8 Extra logic for the decision (timing, area).

Minimizing bus switching (Cont.) Didn’t work because: Largest bus is 8bit. Capacitance less than 1pF. Toggle activity not very high.

Power Reduction in InfoPad

Power Management by Gated Clock Power Management Scheme by Enabling Clock Power Management Scheme by adding Clock Generation block

Method That Works: Pixel Differentials ý Pixel value area locality. ý This is exploited most heavily in compression (save on storage and transmission). ý Most of the functions are linear, able to work on differences. ý The entire algorithm was rewritten (interpolations, filters, matrices, etc.) ý New algorithm differs from original by no more then 1 lsb bit per pixel.

Methodology C++ Simulator Algorithm Image Compare Verilog Simulator RTL Synopsys Netlist P&R Cadence Opus Spice Netlist Epic Powermill Currents, power Image 0.35 Lib Compass

Pixel Difference

Pixel Differentials Algorithm Results

Summary ý Attempted to save power on a battery-operated chip by application specific algorithmic/architectural techniques: Async. Logic, Gated clock, Minimizing bus switching. ý All Attempts failed. These methods may still apply to very large, very fast chips, and on variable load application. ý Successfully applied an algorithmic change, inspired by image compression. It may not work on non-compressible data but works exceptionally well on images. ý Easily saved 80% power, potentially can save more than 90%.

A SINGLE-CHIP DIGITAL CAMERA H. Teresa H. Meng, “Low-Power Wireless Video System”, IEEE Communication Magazine, June, 1998 ◈ Given the recent development in CMOS RF transceiver design, wireless transmission at a bandwidth in excess of 10Mb/s will soon become possible using next-generation CMOS technology. ◈ The design of a low-power large-scale parallel MPEG2 encoder architecture to be used in a single-chip digital CMOS video camera. ◈ The single-chip digital camera architecture includes a 640 x 480 array of CMOS photo diodes, embedded DRAM for storing four frames of color data, and parallel array processor for video signal processing ◈ The parallel processor architecture is designed to implement highly computationally intensive image and video processing tasks such as color conversion, discrete cosine transform(DCT), and motion estimation for MPGE2.

A SINGLE-CHIP DIGITAL CAMERA

Energy per operation at a 1.5V supply in 0.8  m CMOS technology

A SINGLE-CHIP DIGITAL CAMERA ◈ Design Consideration  The proposed architecture considers three algorithms commonly used in video coding standards : red-green-blue(RGB)-to-yellow-ultraviolet (YUV) conversion, discrete cosign transform(DCT), and motion estimation  To reduce power consumption, as many parallel processors as practically feasible should be used to reduce the clock frequency, because a reduced clock frequency implies a lower supply voltage.  For MPEG-2 encoding, the computational demand required for motion estimation(1.6 BOPS for 30 frames/s based on the algorithm proposed by Chalidabhongese and Kuo) limits the number of columns in each processor domain to 16, because otherwise the required clock speed for each processor would be too high for a low-power design

A SINGLE-CHIP DIGITAL CAMERA ◈ PERFORMANCE  In order to sustain this computational demand, each processor is required to run at a clock frequency equal to or higher than 40 MHz.  When implemented in a 0.2  CMOS technology, a 1V supply voltage should be more than enough to support a 40MHz operation  Under these condition, this parallel processor architecture delivers a processing of 1.6 BOPS with a power consumption of 40mW

Vector Quantization Lossy compression technique which exploits the correlation that exists between neighboring samples and quantizes samples together

Complexity of VQ Encoding The distortion metric between an input vector X and a codebook vector C_i is computed as follows: Three VQ encoding algorithms will be evaluated: full search, tree search and differential codebook tree- search.

Full Search Brute-force VQ: the distortion between the input vector and every entry in the code-book is computed, and the codeindex that corresponds to the minimum distortion is determined and sent over to the decoder. For each distortion computation, there are 16 8-bit memory accesses (to fetch the entries in the codeword), 16 subtractions, 16 multiplications, 15 additions. In addition, the minimum of 256 distortion values, which involves 255 comparison operations, must be determined.

Tree-structured Vector Quantization If for example at level 1, the input vector is closer to the left entry, then the right portion of the tree is never compared below level 2 and an index bit 0 is transmitted. Here only 2 x log = 16 distortion calculations with 8 comparisons

Algorithmic Optimization Minimizing the number of operations –example video data stream using the vector quantization (VQ) algorithm distortion metric –Full search VQ exhaustive full-search distortion calculation : 256 value comparison : 255 –Tree-structured VQ binary tree-search some performance degradation distortion calculation : 16 ( 2 x log ) value comparison :

Differential Codebook Tree-structure Vector Quantization The distortion difference b/w the left and right node needs to be computed. This equation can be manipulated to reduce the number of operations.

Algorithmic Optimization –Differential codebook tree-structure VQ modify equation for optimizing operations algorithm # of mem. access full search tree search differential tree search # of mul. # of add. # of sub

Multiplication with Constants Techniques and tools have been developed to scale coefficients so as to minimize the number of 1’s in the coefficients so as to minimize the number of shift-add operations.

Gated clocks to shut down modules when not used.