CS1104 – Computer Organization PART 2: Computer Architecture Lecture 12 Overview and Concluding Remarks

2 Part 2 (and link to Part 1)  Apparently disjoint  In Part 1 you studied digital logic  In Part 2 we made use of the building blocks you studied in Part 1 to design computer architectures  We designed computers at a high level of abstraction  Your ISA, datapath, control unit design, etc. will be passed over to your EE/ECE friend who will “implement” it in silicon

3 Those who will not design computer architecture  This course will (hopefully) help you to write good programs  You have learnt that variables are stored in registers  You know how memory is organized (using pointers in C will no longer be difficult)  You know about spatial locality and its relation to caches  You know that some instructions take more time to execute than others (shift is better than mul)

4 Those who will design computer architecture  More advanced courses will build upon this course  Graduate-level Computer Architecture  Embedded Systems  Parallel Computer Architecture  This is a big and thriving research area

5 Those who will work at a bank  Hopefully you’ll be able to read product literature better and buy better computers for your office

6 What did we study? Topic 1  Performance evaluation  How to evaluate and compare the performance of different computers  How to summarize performance measurements (averages of execution times, normalized execution times, etc.)  Benchmarking (how should good benchmarks be designed)  CPU performance equation (instruction count, clock cycles per instruction, clock cycle time, how are they determined, what is the relationship between them, how do they change, etc.)  Amdahl’s law (lesson: make the common case fast)

7 Topic 2  Instruction set architecture (ISA)  Executing a stored program – basic organization (ALU, instruction and data memory, machine instructions, what is a program counter, how is a program “executed”, etc.)  What is an ISA?  Storage options on the processor (stack, accumulator, register memory, register load-store, etc.) and their advantages and disadvantages  Memory addressing schemes – big and little endian, word alignment, addressing modes like register, immediate, displacement, direct, register indirect, etc. Which are the most common ones among these? What are their relative advantages and disadvantages  Operations in an instruction set (data transfer, arithmetic/logical, control flow, etc)  Encoding an instruction set (variable, fixed and hybrid encodings)  Different possibilities involved in a design and the associated tradeoffs

8 Topic 3  MIPS assembly language programming  Organization (number of registers, their functions, etc.)  Instruction formats (R-format, I-format, J-format) and their associated fields  Addressing modes (register, immediate, displacement, PC- relative)  Control flow (conditional branches, jumps, etc)  Creating and manipulating arrays  Pseudo-instructions  Simple programming

9 Topic 4  Single-cycle control and datapath  The different components – register file, instruction memory, data memory, PC, ALU, etc – their inputs and outputs  Which parts of the datapath are active during the execution of common instructions: R-format instructions like ADD, I-format instructions like ADDI, LW and SW, instructions for conditional branches, J-format instructions  Putting the above pieces of the datapath together to construct the complete datapath  Which control signals have to be active for each instruction execution? For example, what should be the values of the different control signals during the execution of ADD, or Jump, or BEQ?  How should the control unit be designed – link to the Part 1 of this course

10 Topic 5  Multicycle control and datapath  Differences with the single-cycle implementation  Consequences, advantages and disadvantages of multicycle implementations  Breaking an instruction execution into multiple steps – instruction fetch, instruction decode, execution/memory address computation/branch completion, etc.  For different instruction classes like R-format, or LW/SW, or Jump, how does each of the above steps look like?  What are the active control signals during each of the above steps for different instruction classes?  How is the control unit designed?

11 Topic 6  Pipelining  The basic concept of pipelining, ideal speedup, what makes pipelining easy and difficult  Breaking up instruction execution into stages, comparisons with single-cycle and multicycle datapath  Concept of pipeline registers, how do the different execution stages look like for common instructions like LW, when do pipeline registers get written and when are they read  Graphically representing instruction execution in pipelines  Designing the control unit for pipelined datapath, how is it similar to single- cycle datapath  Hazards, types of hazards (structural, data, control)  Why structural hazards do not occur in MIPS  Hardware and software solutions for data hazards  How to avoid RaW hazards in MIPS – forwarding  Conditions for detecting hazards, forwarding hardware, conditions for forwarding  Stalling, conditions  Control hazard, branch prediction  Exceptions NOT included in the syllabus

12 Topic 7  Memory Hierarchy and Caches  Different types of memories, motivation behind hierarchical organization  Concept of temporal and spatial locality  Caches, concept of blocks, hits, misses  Direct mapped caches – index, offset, tag, Total size of a cache (tag + data)  How to map memory addresses to caches  Different kinds of memory organizations and associated cache penalties  Tradeoffs between block size and miss rate  Set-associative caches, locating data in the cache, total size of the cache  Cache replacement policies

13  Only few basic principles  Read the textbook  Make sure that you understand how simple instructions are executed on a datapath and what the values of the corresponding control signals are Seems we studied a lot!

14  50 Marks from Part 1, 50 Marks from Part 2  20 MCQs (10 from Part 1, 10 from Part 2) – 20 Marks  2 long questions from Part 1 – Marks  2 long questions from Part 2 – Marks Examination

15 Best of luck for the examination!