Efficient Power Management for Memory in Soft Real Time Systems Midterm presentation

DRAM Every Chip and rank in the DRAM has several powermodes: Transition in and out of lower power modes needs time read writes are only possible in active mode!

Power saving methods Power aware scheduler Power augmented History Scheduler Throttling Power dynamic transition Power static transition

Power saving methods Power down unused chips (PD) → OS/Memory scheduler should use just minimal needed number of chips Group read write accesses timely – Scheduler has to look at a stack of instructions and reorder them in a reasonable manner Throttle speed/queue

Power saving methods DRAM Processors/Caches Memory Queue Scheduler Read Write Queues Reads/Writes MEMORY CONTROLLER 1.Read/Write instructions are queued in a stack 2.Scheduler (AHB) decides which instruction is preferred 3.Subsequently instructions are transferred into FIFO Memory Queue

Chosen Approach A.Many Power Down mechanism were evolved for DRAM, but usually they just handle two Power Modes – Use all 4 (active, standby, nap, power down) B.Algorithm‘s primary concern is to meet timing constraints C.If no negative influence is expected power down a chip/rank (according to simple algorithm): D.Maybe allow fast „backdoor“ for highest priority tasks – Chips/Ranks where critical tasks are assigned to never power down and are served with FIFO manner E.Throttle commands in Queue to allow better task execution time estimation, reordering mechanism and longer power down times

A. Powering down unused chips Read/Write Queue C:1 - R:1 - B-1 - … C:1 - …. - … C:1 - … - … C:2 - … - … C:1 - … - … C:2 - … - … - C:1 - … - … - C:2 - … - … - Chip 3 Chip 2 K2 epochs later K3 epochs later PM t

A. Reordering Read/Write Queue C:1 - R:1 - B-1 - … C:1 - …. - … C:1 - … - … C:2 - … - … C:1 - … - … C:2 - … - … - C:1 - … - … - C:2 - … - … - Chip 1 Chip 2

Manipulate PM B. Guarantee Soft RT Set Power Mode to result in a shorter estimated execution time then deadline The Transfer function can be estimated by + tt opt Transfer function Controller - Command threshold If timing constraint is violated set a certain threshold for power down

C. Power down used chips with gaps 1For I from 1 to n 2Get Deadline miss for task i 3 If deadline misses > 0 4PM i = 1 // set the power mode of the concerned rank/chip to highest. 5else 6Get Deadline for task i 7Calculate t act for task i 8Set t act (T) < t dl //set T so that t is just shorter then t dl 9Calculate best Energy consumption for tasks 10If optimal Energy PM is higher then optimal Timing PM 10aThen use optimal Energy PM 10bElse use optimal Timing PM 11Get which Rank/Chip wasn’t used for a certain threshold (counting flags) 12Power them down one step 13Assign PM to DRAM Pseudo code Control Algorithm: DRAM example with Matlab Tasks 1- 10: (T,Dl,adr1,adr2, misses)

D. Power down used chips with gaps Tasks power down primary when timing constraints are hold but with reasonable power budget: t fastPM < t opt < dl Energy loop has only little influence EL is mainly concerned with unused chips

E. Throttling Approach “Force memory commands to wait in the memory controller, DRAM structures can remain in low power mode for arbitrarily long periods of time, thereby modulating the DRAM’s average power consumption over some small time interval.”... 10,000 cycles T cycles activestall active stall time T cycles

13 E. Key Difficulty: to determine accurate throttling  Inaccurate throttling  Power consumption is over the budget  Unnecessary performance loss A B Application 1 App. 2

E. Existing Method By Ibrahim Hur and Calvin Lin Model features that we determine Power threshold Number of Reads Number of Writes Bank conflict information System model Compute model coefficients during system design/installation by experiments with various memory access behavior.

15 Monitor Set Power P s = 60W Write Rates Read Rates RAM CtrlController P(n-1) K*Δp(n) RAM Power Calc Throttling: y(n) E. Throttling Mechanism with Feedback Control

E. Power Model Total Power: Detailed information refer to : And DRAMsim Manual at pdf

E. Simulator-DRAMsim+VisTool Device UtilizationUtilization Statistic

Outlook for future work Feedback for change of threshold Reordering Mechanism “Backdoor” Throttling Mechanism which doesn’t violate timing constraints Simulations to show superior RT behavior of memory controller