09/04/971 Xilinx Cadence Alliance Series Technology through Teamwork

09/04/972 Agenda  Product Overview  Design Flow Methodology  XACT to M1 Migration

09/04/973 Product Overview  Cadence FPGA Products  XACT (pre-M1) Cadence Interface  Cadence Releases  Xilinx M1.3 Development System  Xilinx Releases

09/04/974 Cadence FPGA Products Supported in XACTstep 5.2.x, but no longer supported in the Xilinx M1.3 release

09/04/975 XACT Cadence Interface (pre-M1) Effective 11/1/96, Cadence no longer distributes the Xilinx Core tools. Xilinx has exclusive ownership of both maintenance and support of these tools.

09/04/976 Cadence Releases Compatible with Xilinx M1.3 Release

09/04/977 M1 Software Products Cadence interface libraries and netlisters must be obtained from Cadence

09/04/978 M1 Cadence Interface

09/04/979 M1 Cadence Interface

09/04/9710 Xilinx M1 Releases

09/04/9711 Design Flow Methodology  M1 Flow  Schematic Entry  HDL Synthesis  M1 Implementation  Verilog Timing Simulation  Summary

09/04/9712 Xilinx M1 Design Flow Verification Point  Integration D esign S ource  Implementation K nowledge D riven nowledge- D riven  Schematic entry: CONCEPT HDL entry: SYNERGY Interface netlist: EDIF Device Implementation: Xilinx Design Manager & Flow Engine Interface Netlist: Verilog or VHDL Simulator: Verilog-XL or VITAL- compliant simulator (Leapfrog)

09/04/9713 Concept Schematic Flow Concept Unified Sch. Libraries Optional LogiCores LogiBLOX module.v Via HDL_Direct Schematic Design Schematic Entry Genview Symbol Body CONCEPT Constraints File Implementation Tools Knowledge Driven module.ngo Verilog *.v EDIF *.edf CONCEPT2XIL CONCEPT2XIL -sim_only.v file.vf file User-Specified Verilog Testbench Verilog Unified Simulation Libraries Functional Simulation Verilog-XL - netlister from Cadence

09/04/9714 Synergy Synthesis Flow Constraints File module.ngo LogiCores LogiBLOX VLOG2XIL EDIF *.edf User-Specified Verilog Testbench Verilog Unified Simulation Libraries Optional VHDL or Verilog HDL Post-Synthesis Functional Simulation RTL Behavioral Simulation Implementation Tools Knowledge Driven HDL Entry SYNERGY Functional Simulation Verilog-XL Synergy Synthesis Libraries.NCF Timing constraints Structural Verilog *.v - netlister from Cadence

09/04/9715 HDL Entry LogiBLOX Timing Concept/Synergy Mixed Mode Flow SYNERGY Schematic Entry Genview Symbol Body CONCEPT Concept Unified Schematic Libraries.UCF Constraints File Implementation Tools Knowledge Driven EDIF *.edf CONCEPT2XIL CONCEPT2XIL -sim_only.v file.vf file User-Specified Verilog Testbench Verilog Unified Simulation Libraries Functional Simulation Verilog-XL Synergy Synthesis Libraries Structural Verilog *.v Concept top level schematic Structural Verilog *.v.NCF.NGO - netlister from Cadence

09/04/9716 Generic Mixed Mode Flow Constraints File Concept Unified Schematic Libraries module.ngomodule.v Via HDL_Direct Non-schematic block: EDIF, XNF or NGO Optional LogiCores LogiBLOX Schematic Entry Genview Symbol Body CONCEPT Implementation Tools Knowledge Driven EDIF CONCEPT2XIL XIL2CDS Board-level Simulation Pin SDF Testfixture Verilog Simprim Library Timing Simulation Verilog-XL Functional Simulation Verilog-XL EDIF, XNF, or NGO NGDBuild NGD2VER - netlister from Cadence

09/04/9717 Implementation Tools Knowledge Driven Synopsys/Verilog Flow Constraints File module.ngo LogiCores LogiBLOX module.v DC2NCF User-Specified Verilog Testbench Optional Synergy Synthesis Libraries VHDL or Verilog HDL RTL Behavioral Simulation Functional Simulation Verilog-XL HDL Entry Component Instantiation.sxnf.dc FPGA Compiler or Design Compiler.sedif

09/04/9718 Xilinx Implementation Flow Implementation K nowledge D riven nowledge- D riven  NGDBuild.ngd NGDAnno routed.nga MAP.ncd BITGEN routed.bit PAR routed.ncd To Post-Implementation Timing Simulation.edf To Design Download.xnf.ngo To Simprim-Based Functional Sim. To Post-Map Timing Sim. NGD2VER

09/04/9719 Timing Simulation (Verilog) NGD2VER -tf -ul -pf.pin.nga Verification Point  -tf: Generate testfixture -ul: Include `uselib -pf: Generate pin file - (for board-level sim).sdf.tv.v User-Specified Verilog Testbench Verilog Simprim Library For Board-level Simulation Chips_prt Body Timing Simulation Verilog-XL Edit XIL2CDS - netlister from Cadence

09/04/9720 Timing Simulation (VHDL) NGD2VHDL -tb.nga Verification Point  -tb: Generate testfixture.sdf.tb.vhd User-Specified VHDL Testbench ** VHDL Simprim Library Timing Simulation Leapfrog Edit [] ** This Library must be compiled by user

09/04/9721 Flow Summary Implementation Tools Knowledge Driven Timing Simulation Verilog-XL Schematic Entry CONCEPT HDL Entry SYNERGY EDIF VLOG2XILConcept2XIL XIL2CDS Functional Simulation Verilog-XL Board-level Simulation Pin SDF Testfixture Verilog Concept2XIL -sim_only Verilog Verilog Unified Simulation Libraries Verilog Concept Unified Schematic Libraries Verilog Simprim Library Synergy Synthesis Libraries - netlister from Cadence

09/04/9722 Cadence Methodology Changes  Cadence 5.X Environment —lib/cell/view/file structure  PIC flow —Verilog as intermediate format —EDIF interface to Xilinx —Standard HDL Direct methodology

09/04/9723 XACT to M1 Migration  ITERATED INSTANCES instead of SIZE property (See HDL Direct User Guide) —modify PATH property —Ex. PATH = I4 changes to PATH=I4(2:0) to indicate 3 copies of an object  SCALD to HDL Direct schematic conversion (REQUIRED)  X-BLOX to LogiBLOX conversion —all X-BLOX modules must be replaced with their LogiBLOX counterparts

09/04/9724 XACT to M1 Migration  Iterated Instances instead of SIZE property —Ex. Set PATH = I4(2:0) to indicate 3 copies of an object with PATH value of I4 PATH = I4(2:0) PATH = I4 3 instances DQDQ

09/04/9725 XACT to M1 Migration  Tapping Bus Bits —renaming of bits not allowed ctrl2 ctrl1 ctrl0 ctrl **** WRONG! **** (bits renamed, alias_bit error) CORRECT ctrl

09/04/9726 XACT to M1 Migration  Other “GOTCHA’s”: —MERGE bodies--all nets must be named —Name of each design subblock must match the corresponding SCALD directory name ctrl

09/04/9727 M1 SCALD to HDL Direct Conversion

09/04/9728 M1 SCALD to HDL Direct Conversion

09/04/9729 X-BLOX to LogiBLOX Conversion  Recommended method: Replace all X-BLOX components with LogiBLOX modules —Generate LogiBLOX module –.v (gate level netlist for simulation only) –.NGO (for implementation) –Verilog template (for instantiation in Verilog) — Create symbol body (schematics only) –genview in Concept –Add: parameter cds_action=“ignore”; —Instantiate module in your design

09/04/9730 Integrating LogiBLOX modules  Run LogiBLOX standalone: —lbgui (select “cadence” as vendor)  Generate symbol body from.v file —genview -i -v logic body verilog  Add line to block/logic/verilog.v module: —parameter cds_action = “ignore”;  Copy.ngo file to Xilinx run directory —(xilinx.run, by default)

09/04/9731 X-BLOX to LogiBLOX Conversion  Alternate Method (short-term solution only) —Process design in XACT down to.XTF — Use.XTF as input to M1 Core tools —Disadvantages –No support for new architecture features –No support for XNF format will be available in future M1.5 release

09/04/9732 New Libraries  M1 Concept Unified Library  M1 Verilog Unified Library  M1 SIMPRIM Verilog Library  M1 Synergy Libraries (available from Cadence only)  No Composer support

09/04/9733 New Libraries  Concept Unified —$XILINX/cadence/data/xce (e.g. xce4000ex) —No support for SIZE property –use Iterated Instances —compatible with pre-M1 Concept Unified libraries –shape and size of symbols –pin locations –component and pin names

09/04/9734 New Libraries  Verilog Unified simulation library —$XILINX/cadence/data/ verilogxce______ (e.g., verilogxce4000ex) —for HDL Direct functional simulation only —no timing checks

09/04/9735 New Libraries  SIMPRIM Verilog libraries —included as part of Xilinx M1 Core —generic, architecture-independent —located in $XILINX/verilog/data

09/04/9736 New Libraries  SIMPRIM Verilog libraries —support all post-NGDBUILD simulation –post-NGDBUILD (functional, gate-level) –post-MAP timing (optional) –post-PAR (post-route) timing —library primitive naming system –X_FF.vmd (flip-flop) –X_BUF.vmd (buffer)

09/04/9737 Concept Setup Files  master.local  design.wrk  global.cmd  cds.lib  startup.concept

09/04/9738 master.local  points to location of Xilinx Concept libraries file_type = master_library; “xce4000ex” ‘/tools/xilinx/cadence/data/xce4000ex/xce4000ex.lib’; “xce4000e” ‘/tools/xilinx/cadence/data/xce4000e/xce4000e.lib’; “xce5200” ‘/tools/xilinx/cadence/data/xce5200/xce5200.lib’; “xce3000” ‘/tools/xilinx/cadence/data/xce3000/xc3000.lib’; “xce7000” ‘/tools/xilinx/cadence/data/xce7000/xce7000.lib’; “xce9500” ‘/tools/xilinx/cadence/data/xce9500/xce9500.lib’; end. *Note: XC5200 and XC3000 architectures are not supported in the M1.3 core tools

09/04/9739 design.wrk  Concept project library file FILE_TYPE = LOGIC_DIR; "UNNAMED" 'unnamed'; "MYBLOCK" 'myblock'; END.

09/04/9740 cds.lib  Concept 5.x library file define xce4000ex_syn /tools/xilinx/cadence/data/xce4000ex_syn define xce4000e_syn /tools/xilinx/cadence/data/xce4000e_syn define xce5200_syn / tools/xilinx/cadence/data/xce5200_syn define xce3000_syn /tools/xilinx/cadence/data/xce3000_syn define xce7000_syn /tools/xilinx/cadence/data/xce7000_syn define xce9000_syn /tools/xilinx/cadence/data/xce9000_syn *Note: XC5200 and XC3000 architectures are not supported in the M1.3 core tools

09/04/9741 global.cmd  Concept project library alias file master_library "./master.local" ; library "xce4000ex", "hdl_direct_lib", "xcepads", "standard" ; use "design.wrk" ; root_drawing "unnamed" ;

09/04/9742 startup.concept (reinforces HDL Direct naming conventions) set hdl_direct on set hdl_checks on set check_signames on set check_net_names_hdl_ok on set check_port_names_hdl_ok on set check_symbol_names_hdl_ok on set capslock_off * (preserves case, may be important for TIMESPECs) runopl /products/cds.ver97a/tools/fet/concept/hdl_direct /bin/autosym

09/04/9743 Concept Properties  Properties are specified as: name=value —Use xilinx.pff in $XILINX/cadence/data as a guide to property specification format —Boolean –must be set to TRUE or FALSE –Example: FAST=TRUE (output slew rate) – KEEP=TRUE (“X” in XACT) —Normal –Location constraints (LOC=P6) –Timegrps(GRP01=mygrp) –(names are case-sensitive if you specify “set caps_lock_off” in startup.concept)

09/04/9744 Concept Properties  Part type property —“PART=XC4028EX-3-PG299” —Attach to CONFIG symbol: CONFIG PART=XC4028EX-3-PG299

09/04/9745 M1 Global Signal Support

09/04/9746 Global signal support in M1.2/M1.3  M1.2.11: —glbl.v contains declarations of global wires in “glbl” module —signals referenced as glbl.gsr, glbl.gts, etc.  M1.3.x: —Verilog macros in the test fixture assign the names of the global signals —`define GSR_SIGNAL sig_name

09/04/9747 Global signals in M1.2  M —module glbl in separate glbl.v file –global signals declared as wires: –wire gsr; // 4k –wire gts; // 4k, 5k* –wire prld; // 7k, 9k –wire gr; // 3k*, 5k* * 3K and 5K not supported in M1.3 core tools —pre-route HDL Direct simulation netlist: X_FF inst_name2 (.IN ….RST(glbl.gsr));

09/04/9748 Global signals in M1.2 —post-NGDBUILD simulation: –glbl.gsr OR’d with local reset: X_OR2 inst_name1 (.IN0(glbl.gsr),.IN1(local_clr),.out(xxxx.GSR.OR)); X_FF inst_name2 (.IN(aaaa),.CLK(bbbb),.CE(cccc),.SET(ssss) ….RST(xxxx.GSR.OR)); —Testbench: –force glbl.gsr = 1;

09/04/9749 Global signals in M1.2 — Verilog-XL command line: verilog design.tv design.v glbl.v * glbl.v not supported in M1.3

09/04/9750 Global signals in M1.3  Utilizes Verilog macros*  Unified Verilog library modifications to support the Verilog macros  Test fixture support *Verilog macro: `define xx_SIGNAL where “xx” = GSR, GR, GTS, or PRLD

09/04/9751 Global signals in M1.3-- LIBRARIES  Global Reset support (4K) —Each 4K Verilog Unified library register model contains the following block of code to model GSR: `ifdef GSR_SIGNAL wire GSR = `GSR_SIGNAL; `else wire GSR; `endif

09/04/9752 Global Tri-state in M1.3-- LIBRARIES  Global Tri-state support (4K) —Each Verilog Unified library output buffer model contains the following block of code to model GTS: `ifdef GTS_SIGNAL wire GTS = `GTS_SIGNAL; `else wire GTS; `endif

09/04/9753 Global signals in M1.3: TEST FIXTURES  global reset (4K) —(no Startup block) module test; reg GSR; `define GSR_SIGNAL GSR design uut ( ); initial begin `GSR_SIGNAL = 1; #100 `GSR_SIGNAL = 0;

09/04/9754 Global signals in M1.3: TEST FIXTURES  global reset (3K, 5K)* reg GR; `define GR_SIGNAL GR `GR_SIGNAL = 1; #100 `GR_SIGNAL = 0; *3K and 5K are mentioned here for reference purposes only-- they are not supported in the M1.3 release

09/04/9755 Global Tri-state signals in M1.3: TEST FIXTURES  global tri-state (4K, 5K*) reg GTS; `define GTS_SIGNAL GTS `GTS_SIGNAL = 1; #100 `GTS_SIGNAL = 0;  global reset (7K, 9K ) reg PRLD; `define PRLD_SIGNAL PRLD `PRLD_SIGNAL = 1; #100 `PRLD_SIGNAL = 0; * 5K is mentioned here for reference purposes only, not supported in M1.3 release

09/04/9756 Summary: M1.3 LIBRARY support for Xilinx globals * 3K and 5K mentioned here for reference purposes only, not supported in M1.3 release

09/04/9757 M1.3 TEST FIXTURE support for Xilinx globals (XC5200*) * 5K is mentioned here for reference purposes only, not supported in M1.3 release

09/04/9758 M1.3 TEST FIXTURE support for Xilinx globals ( XC4000)

09/04/9759 M1.3 TEST FIXTURE support for Xilinx globals ( XC3000*) * 3K is mentioned here for reference purposes only, not supported in M1.3 release

09/04/9760 Cadence Survival Kit Use in case of emergency

09/04/9761 Documentation Xilinx manuals : M1 QuickStart Guide M1 Conversion Guide M1 Cadence Interface/Tutorial Guide Key Cadence manuals: Concept User Guide HDL Direct User Guide, Appendix C (SCALD to HDL Direct Conversion)

09/04/9762 Where to go for help  Xilinx Support —Tech support: or —Customer service: —Web: –Answers Search –Expert Pages / Cadence  Cadence Support —Tech support: cadenc2 or —Web: (must be registered customer)