Measurements of the first ON Semiconductor production wafers at Udine Prepared by Diego Cauz on behalf of the group of Udine April 2004 Udine.

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Presentation transcript:

Measurements of the first ON Semiconductor production wafers at Udine Prepared by Diego Cauz on behalf of the group of Udine April 2004 Udine

Atlas Pixel Italia Apr Measurement speed-up Doctor Sergey Gorokhov is back in Udine since April 14th. He will stay for 3 months

Atlas Pixel Italia Apr ON-Semic wafers in Udine We have received 11 ON Semiconductor wafers in April: –2 partially measured for quick shipping to AMS

Atlas Pixel Italia Apr Visual inspection (VIS)(1/3) Y-Y correct Y-Y correct Y-Y correct Y-Y correct Y-Y correct Mask Align (H-V) Wafer n-side L n-side R p-side L p-side R ID marking

Atlas Pixel Italia Apr Visual inspection (VIS)(2/3) Y-Y correct Y-Y correct Y-Y correct Y-Y correct Y-Y correct Y-Y correct Mask Align (H-V) Wafer n-side L n-side R p-side L p-side R ID marking Bad passivation vernier in the 4th vernier pair on all 4 monitors, both H and V, all wafers. See next slide

Atlas Pixel Italia Apr 20046

7 Many defects, probably scratches on the tiles of Tile 1: 8 scr.s -93 pix Tile 2: 4 scr.s -20 pix Tile 3: 9 scr.s -122 pix

Atlas Pixel Italia Apr Wetting residue

Atlas Pixel Italia Apr WaferVernier Passiv. Bump openings badbad* bad bad bad bad WaferVernier Passiv. Bump openings badgood badgood badgood bad~good bad~good bad Visual inspection (VIS)(3/3) *: AMS communication ~: bad on limited areas

Atlas Pixel Italia Apr

Atlas Pixel Italia Apr

Atlas Pixel Italia Apr Thickness measurement (THI) Wafer th1 th2  (  m) 220  m < th < 260  m  th < 10  m Wafer th1 th2  (  m)

Atlas Pixel Italia Apr I-V on diode w/ guard ring (IVD) Wafer Vbd (V) Iop (nA) Iop = I(Vop)Vbd = max V(I < 25 nA) Wafer Vbd (V) Iop (nA)

Atlas Pixel Italia Apr C-V on diode w/ guard ring (CVD) (1/2) Vdep Cdep Vop  Wafer (V) (pF) (V) (  cm) 30 < Vdep (V) < <  (  cm) < 5000 Vdep = V(kink in C-V curve) Cdep = C(Vdep) Vop = max(150 V, Vdep + 50 V) Measurement very noisy. One cable found defective. Large incertitude on Vdep.

Atlas Pixel Italia Apr C-V on diode w/ guard ring (CVD) (2/2) Vdep Cdep Vop  Wafer (V) (pF) (V) (  cm) 30 < Vdep (V) < <  (  cm) < 5000 Vdep = V(kink in C-V curve) Cdep = C(Vdep) Vop = max(150 V, Vdep + 50 V) See next slide

Atlas Pixel Italia Apr

Atlas Pixel Italia Apr I-V on tiles (1/2) Wafer Vop (V) Vbd (V) S good tiles Vbd > VopS = I(Vop) / I(Vop-50) < x x-2-x x x x

Atlas Pixel Italia Apr I-V on tiles (2/2) Wafer Vop (V) Vbd (V) S good tiles Vbd > VopS = I(Vop) / I(Vop-50) < x x x x x-x-x x-2-x Bad I-t

Atlas Pixel Italia Apr I-V on SC’s Vbd > VopS = I(Vop) / I(Vop-50) < 2 Wafer good/total Only half of the SC’s are being measured / / / / / / / / / / /4 Wafer good/total

Atlas Pixel Italia Apr I-V on MC’s Vbd > VopS = I(Vop) / I(Vop-50) < 2 Wafer good/total Only half of the MC’s are being measured / / / / / / / / / / /2 Wafer good/total

Atlas Pixel Italia Apr I-t on good tiles (ITS) Wafer-tile S S = Iend / Istart < bad

Atlas Pixel Italia Apr I-V on MOS (BOX) Wafer Vbd (V) delay = 4 s Vbd = max V(I 50 V Wafer Vbd (V)

Atlas Pixel Italia Apr C-V on MOS (COX) Wafer Cox (pF) Cmin (pF)C FB (pF) V FB (V) Cox = CmaxV FB = V(C nearest to C FB )

Atlas Pixel Italia Apr I-V on gate-controlled diode (IVG) Itop = I(V FB +3 V) Ibot = I(V FB – 3 V) Wafer Itop (pA) Ibot (pA)Iox(pA)

VFB is around 16 V V FB is around 4 V COX, IVG discrepancy

Atlas Pixel Italia Apr I-Vg on MOSFET (MFE) Wafer Vth (V) p-dose (x cm -2 ) bad- 2.2 < p (10 12 cm -2 ) < 3.5Vth = max V(I 0 V th is usually good, but I beyond threshold is very low. See next slide.

Atlas Pixel Italia Apr

Atlas Pixel Italia Apr Vpix-V on punch-thru structure (PUT) Wafer Vpt (V) Vpt >3 V bad Wafer Vpt (V)

Atlas Pixel Italia Apr Conclusions 11 wafers are being measured –Missing measurements: VIS, PLA –Some measurements need to be done again Wafer quality : –bad passivation in the mask alignment monitor for all 4th vernier pair, wafers , –Many scratches on the tiles of –Bad bump pads for (and ) –wafer does not pass MFE test –wafer , have only one good tile –wafer has no good tile –Almost all wafers do not pass PUT test

Atlas Pixel Italia Apr Wafer acceptance reasons * BO,  BO,PUT,1GT BO,PUT BO,  BO,PUT Wafer acceptance reasons PUT PUT ,PUT PUT It,PUT,0GT * ,1GT Conclusions

Atlas Pixel Italia Apr Project Progress Tracking Dortmund 145/250 58% New Mexico 0/250 0% Prague 250/250100% Udine 212/250 84% This tool is not trustable. Laboratorytiles meas/totalpercent

Atlas Pixel Italia Apr Tile pool In reality the 4 labs have received a total of 1121 tiles, 1060 of which have been accepted: –Dortmund:250 –NM:265 –Prague:250 –Udine:212 The missing tiles are to be finished measuring by Udine (14 wafers) and Dortmund.