Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Topics n Pseudo-nMOS gates. n DCVS gates. n Domino gates.

Slides:

Advertisements

Similar presentations

ECE555 Lecture 5 Nam Sung Kim University of Wisconsin – Madison

Advertisements

Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR Topics n Combinational logic functions. n Static complementary logic gate structures.

Topics Electrical properties of static combinational gates:

FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR Gate Design n Static complementary logic gate structures. n Switch logic. n Other.

Modern VLSI Design 4e: Chapter 5 Copyright  2008 Wayne Wolf Topics n Memory elements. n Basics of sequential machines.

Introduction to CMOS VLSI Design Lecture 19: Design for Skew David Harris Harvey Mudd College Spring 2004.

S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN1600) Lecture 21: Dynamic Combinational Circuit Design Prof. Sherief Reda Division of.

Chapter 09 Advanced Techniques in CMOS Logic Circuits

Introduction to CMOS VLSI Design Clock Skew-tolerant circuits.

Clock Design Adopted from David Harris of Harvey Mudd College.

Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania ECE VLSI Circuit Design Lecture 9 - Combinational.

Designing Combinational Logic Circuits: Part2 Alternative Logic Forms:

Modern VLSI Design: Chapter 3 Copyright  1998 Prentice Hall PTR Topics n Combinational logic functions n Static complementary logic gate structures.

Modern VLSI Design 2e: Chapter 4 Copyright  1998 Prentice Hall PTR Topics n Switch networks. n Combinational testing.

Modern VLSI Design 2e: Chapter4 Copyright  1998 Prentice Hall PTR.

Copyright 2001, Regents of University of California Lecture 18: 04/0703 A.R. Neureuther Version Date 04/03/03 EECS 42 Intro. electronics for CS Spring.

Lecture #24 Gates to circuits

Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Topics n Memory elements. n Basics of sequential machines.

S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 22: Material Review Prof. Sherief Reda Division of Engineering, Brown University.

Lecture #25 Timing issues

Introduction to CMOS VLSI Design Circuit Families.

S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 21: Differential Circuits and Sense Amplifiers Prof. Sherief Reda Division.

Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 13 1 ELEC 5270/6270 Fall 2007 Low-Power Design of Electronic Circuits Pseudo-nMOS, Dynamic CMOS and Domino.

Topics Combinational logic functions.

Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR Topics n Memories: –ROM; –SRAM; –DRAM. n PLAs.

INEL Dynamic logic timing sequence Figure (a) Basic structure of dynamic-MOS logic circuits. (b) Waveform of the clock needed to operate the.

Digital CMOS Logic Circuits

12/10/2004EE 42 fall 2004 lecture 421 Lecture #42: Transistors, digital This week we will be reviewing the material learned during the course Today: review.

Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic COMBINATIONAL LOGIC.

VLSI Digital Systems Design Alternatives to Fully-Complementary CMOS Logic.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Topics n Combinational logic functions. n Static complementary logic gate structures.

1 Delay Estimation Most digital designs have multiple data paths some of which are not critical. The critical path is defined as the path the offers the.

MOS Transistors The gate material of Metal Oxide Semiconductor Field Effect Transistors was original made of metal hence the name. Present day devices’

1 VLSI Design SMD154 LOW-POWER DESIGN Magnus Eriksson & Simon Olsson.

EE415 VLSI Design DYNAMIC LOGIC [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Topics n Basic fabrication steps. n Transistor structures. n Basic transistor behavior.

EE 447 VLSI Design Lecture 8: Circuit Families.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Topics n Latches and flip-flops. n RAMs and ROMs.

Ratioed Circuits Ratioed circuits use weak pull-up and stronger pull-down networks. The input capacitance is reduced and hence logical effort. Correct.

FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Topics n Combinational logic functions. n Static complementary logic gate structures.

DCSL & LVDCSL: A High Fan-in, High Performance Differential Current Switch Logic Families Dinesh Somasekhaar, Kaushik Roy Presented by Hazem Awad.

Modern VLSI Design 2e: Chapter 3 Copyright  1998 Prentice Hall PTR Topics n Electrical properties of static combinational gates: –transfer characteristics;

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Topics n Combinational network delay. n Logic optimization.

Notices You have 18 more days to complete your final project!

Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week5-1 Lecture 14 CMOS Logic Gates Feb. 5, 2003.

Modern VLSI Design 3e: Chapters 3 & 8Partly from 2002 Prentice Hall PTR week6-1 Lectures 16 Transfer Characteristics (Delay and Power) Feb. 10, 2003.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Topics n Pseudo-nMOS gates. n DCVS logic. n Domino gates. n Design-for-yield. n Gates as IP.

Lecture 10: Circuit Families. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 10: Circuit Families2 Outline  Pseudo-nMOS Logic  Dynamic Logic  Pass Transistor.

VLSI Design Lecture 5: Logic Gates Mohammad Arjomand CE Department Sharif Univ. of Tech. Adapted with modifications from Wayne Wolf’s lecture notes.

Advanced VLSI Design Unit 04: Combinational and Sequential Circuits.

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Topics n Layouts for logic networks. n Channel routing. n Simulation.

Introduction to CMOS VLSI Design Lecture 9: Circuit Families

Dynamic Logic Dynamic Circuits will be introduced and their performance in terms of power, area, delay, energy and AT2 will be reviewed. We will review.

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 1 Digital Integrated Circuits A Design Perspective Designing Combinational Logic Circuits.

Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week3-1 Lectures 6, 7 and 8 Transistor Function Jan. 17, 20 and 22, 2003.

FPGA-Based System Design: Chapter 2 Copyright  2004 Prentice Hall PTR Topics n Logic gate delay. n Logic gate power consumption. n Driving large loads.

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Topics n Wire delay. n Buffer insertion. n Crosstalk. n Inductive interconnect.

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Topics n Electrical properties of static combinational gates: –transfer characteristics;

CMOS Logic Gates. NMOS transistor acts as a switch 2 When gate voltage is 0 V No channel is formed current does not flow easily “open switch” When gate.

EE534 VLSI Design System Summer 2004 Lecture 12:Chapter 7 &9 Transmission gate and Dynamic logic circuits design approaches.

1 Dynamic CMOS Chapter 9 of Textbook. 2 Dynamic CMOS  In static circuits at every point in time (except when switching) the output is connected to either.

EE141 Combinational Circuits 1 Chapter 6 (I) Designing Combinational Logic Circuits Dynamic CMOS LogicDynamic CMOS Logic V1.0 5/4/2003.

Static Logic vs. Pseudo-nMOS Static Logic includes pull-up and pull-down networks - 2n transistors for n-input function. Pseudo-nMOS - n+1 transistors.

EE 466/586 VLSI Design Partha Pande School of EECS Washington State University

CMOS LOGIC STRUCTURE. 1.CMOS COMPLEMENTARY LOGIC CMOS is a tech. for constructing IC. CMOS referred to as Complementary Symmetry MOS(COS-MOS) Reason:

Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved.

Subject Name: Fundamentals Of CMOS VLSI Subject Code: 10EC56

332:578 Deep Submicron VLSI Design Lecture 14 Design for Clock Skew

Presentation transcript:

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Topics n Pseudo-nMOS gates. n DCVS gates. n Domino gates.

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Pseudo-nMOS n Uses a p-type as a resistive pullup, n-type network for pulldowns. Always on. about

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Characteristics n Consumes static power. n Has much smaller pullup network than static gate. n Pulldown time is longer because pullup is fighting.

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Output voltages n Logic 1 output is always at V DD. n Logic 0 output is above Vss. n V OL = 0.25 (V DD - V SS ) is one plausible choice.

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Producing output voltages n For logic 0 output, pullup and pulldown form a voltage divider. n Must choose n, p transistor sizes to create effective resistances of the required ratio. n Effective resistance of pulldown network must be computed in worst case—series n- types means larger transistors.

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Transistor ratio calculation n In steady state logic 0 output: –pullup is in linear region,V ds = V out - (V DD - V SS ) ; –pulldown is in saturation. n Pullup and pulldown have same current flowing through them.

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Transistor ratio, cont’d. n Equate two currents with pull-down transistor in saturation and pull-up in linear region: –I dp = I dd. n Using 0.5 mm parameters, 3.3V power supply: –W p /L p / W n /L n = 3.9.

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR DCVS logic n DCVSL = differential cascode voltage logic. n Static logic—consumes no dynamic or static power. n Uses latch to compute output quickly. n Requires true/complement inputs, produces true/complement outputs. n The cascode (sometimes verbified to cascoding) is a universal technique for improving analog circuit performance, applicable to both vacuum tubes and transistors. The word was first used in an article by F.V. Hunt and R.W. Hickman in 1939, in a discussion for application in low-voltage stabilizers. They proposed a cascade of two triodes (first one with common cathode, the second one with common grid) as a replacement of a pentode. n

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR DCVS structure

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR DCVS operation n Exactly one of true/complement pulldown networks will complete a path to the power supply. n Pulldown network will lower output voltage, turning on other p-type, which also turns off p-type for node which is going down.

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR DCVS example

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Precharged logic n Precharged logic uses stored charge to help evaluation. n Precharge node, selectively discharge it. n Take advantage of higher speed of n-types. n Requires multiple phases for evaluation.

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Domino logic n Uses precharge clock to compute output in two phases: –precharge; –evaluate. n Is not a complete logic family—cannot invert.

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Domino gate structure Domino OR gate

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Domino phases Controlled by clock . n Precharge: p-type pullup precharges the storage node; inverter ensures that output goes low. n Evaluate: storage node may be pulled down, so output goes up.

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Domino buffer n Output inverter is needed for two reasons: –make sure that outputs start low, go high so that domino output can be connected to another domino gate; –protects storage node from outside influence.

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Domino operation

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Domino effect Gate outputs fall in sequence: gate 1gate 2gate 3

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Monotonicity n Domino gates inputs must be monotonically increasing: glitch causes storage node to discharge.

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Output buffer n Inverting buffer isolates storage node. Storage node and inverter have correlated values.

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Using domino logic n Can rewrite logic expression using De Morgan’s Laws: –(a + b)’ = a’b’ –(ab)’ = a’ + b’ n Add inverters to network inputs/outputs as required.

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Domino and stored charge n Charge can be stored in source/drain connections between pulldowns. n Stored charge can be sufficient to affect precharge node. n Can be averted by precharging the internal pulldown network nodes along with the precharge node.

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Homework Sets 3-4 Homework Set 3: Problems 2-13,2-19,2,pp Problems 3-1(c), 3.2(d), 3.7, 3.9, 3.12 pp Due, October 16, Homework Set 4: Problems 3-15, 3-16, 3.19(b), 3.20(b), p Due, October 23, 2006.