CS/EE 3700 : Fundamentals of Digital System Design Chris J. Myers Lecture 3: Implementation Technology Chapter 3

Figure 3.1 Logic values as voltage levels

Figure 3.2 NMOS transistor as a switch x = "low" x = "high" (a) A simple switch controlled by the input x Gate Source Drain Substrate (Body) (b) NMOS transistor V G V V S D (c) Simplified symbol for an NMOS transistor Figure 3.2 NMOS transistor as a switch

Figure 3.3 PMOS transistor as a switch x = "high" x = "low" (a) A switch with the opposite behavior of Figure 3.2 a Gate Drain Source V DD Substrate (Body) (b) PMOS transistor V G V V S D (c) Simplified symbol for an PMOS transistor Figure 3.3 PMOS transistor as a switch

Figure 3.4 NMOS and PMOS transistors in logic circuits V D V = 0 V V D D V G V = 0 V S Closed switch Open switch when V = V when V = 0 V G DD G (a) NMOS transistor V = V V V S DD DD DD V G V V V = V D D D DD Open switch Closed switch when V = V when V = 0 V G DD G (b) PMOS transistor Figure 3.4 NMOS and PMOS transistors in logic circuits

Figure 3.5 A NOT gate built using NMOS technology V DD R R + 5 V - V V f f V V x x (a) Circuit diagram (b) Simplified circuit diagram x f x f (c) Graphical symbols Figure 3.5 A NOT gate built using NMOS technology

Figure 3.6 NMOS realization of a NAND gate V DD V f V x 1 x x f 1 2 1 V x 2 1 1 1 1 1 1 (a) Circuit (b) Truth table x x 1 1 f f x x 2 2 (c) Graphical symbols Figure 3.6 NMOS realization of a NAND gate

Figure 3.7 NMOS realization of a NOR gate

Figure 3.8 NMOS realization of an AND gate V V DD DD V f A V x 1 x x f 1 2 V x 2 1 1 1 1 1 (a) Circuit (b) Truth table x x 1 1 f f x x 2 2 (c) Graphical symbols Figure 3.8 NMOS realization of an AND gate

Figure 3.9 NMOS realization of an OR gate

Figure 3.10 Structure of an NMOS circuit

Figure 3.11 Structure of a CMOS circuit

Figure 3.12 CMOS realization of a NOT gate V DD T 1 V V x f x T T f 1 2 T 2 on off 1 1 off on (a) Circuit (b) Truth table and transistor states Figure 3.12 CMOS realization of a NOT gate

Figure 3.13 CMOS realization of a NAND gate Find PUN and PDN using DeMorgan’s law Figure 3.13 CMOS realization of a NAND gate

Figure 3.14 CMOS realization of a NOR gate Find PUN and PDN using DeMorgan’s law Figure 3.14 CMOS realization of a NOR gate

Figure 3.15 CMOS realization of an AND gate

Figure 3.16 A CMOS complex gate f = x1’ + x2’ x3’ Figure 3.16 A CMOS complex gate

Figure 3.17 A CMOS complex gate f = x1’ + (x2’ + x3’) x4’ Figure 3.17 A CMOS complex gate

Figure 3.18 Voltage levels in a CMOS circuit

Figure 3.19 Interpretation of voltage levels x x f 1 2 1 x 1 1 1 f x 2 1 1 V V V x x f 1 2 1 1 L L H L H H (b) Positive logic truth table and gate symbol H L H H H L x x f 1 2 (a) Voltage levels 1 1 x 1 1 f x 2 1 1 (c) Negative logic truth table and gate symbol Figure 3.19 Interpretation of voltage levels

Figure 3.20 Interpretation of voltage levels x x f 1 2 x 1 1 f x 2 1 V V V x x f 1 1 1 1 2 L L L L H L (b) Positive logic H L L H H H x x f 1 2 (a) Voltage levels 1 1 1 x 1 1 1 f x 1 1 2 (c) Negative logic Figure 3.20 Interpretation of voltage levels

Figure 3.43 a NMOS transistor when turned off V = V G SiO 2 V = V S V D ++++++ ++++ ++++++ ++++++ +++ ++++++ ++++++ ++++++ ++++++ ++++++ +++++++++++ ++++++ ++++++ +++++++++++ +++++++++ Substrate (type p) +++++++++ Source (type n) Drain (type n) (a) When V = 0 V, the transistor is off GS Figure 3.43 a NMOS transistor when turned off

Figure 3.43 b NMOS transistor when turned on V DD V = 5 V G SiO 2 V = V S V = V D ++++++ ++++ +++ ++++++ ++++++ ++++++ +++++++++++ +++++++++++++++++ +++++++++ ++ +++++++ ++++++++++ Channel (type n) (b) When V = 5 V, the transistor is on GS Figure 3.43 b NMOS transistor when turned on

Figure 3.44 Current-voltage relationship in the NMOS transistor D Triode Saturation ID = kn’ W/L [ (VGS – VT)VDS – ½ VDS^2] ID = ½ kn’ W/L (VGS – VT)^2 V – V GS T V DS Figure 3.44 Current-voltage relationship in the NMOS transistor

Figure 3.45 Voltage levels in the NMOS inverter DD DD R V f I V = V stat f OL V R x DS RDS = VDS / ID = 1/ [kn’ W/L (VGS – VT)] Vf = VDD RDS / (RDS + R) See examples 3.4 and 3.5 (a) NMOS NOT gate (b) V = 5 V x Figure 3.45 Voltage levels in the NMOS inverter

Figure 3.46 Voltage transfer characteristics for the CMOS inverter = V OH DD Slope = – 1 V = V OL V V V ( V – V ) V T IL IH DD T DD V x V — DD 2 Figure 3.46 Voltage transfer characteristics for the CMOS inverter

(a) A NOT gate driving another NOT gate 1 2 A x f (a) A NOT gate driving another NOT gate NML = VIL – VOL NMH = VOH - VIH

Figure 3.47 Parasitic capacitance in integrated circuits tp = C dV / ID = C Vdd/2 / ID = 1.7C / kn’ W/L Vdd Figure 3.47 Parasitic capacitance in integrated circuits

Figure 3.48 Voltage waveforms for logic gates

Figure 3.49 Transistor sizes

V V R V I V = V V R V = 5 V V T V V T DD DD f stat x x DD f OL x f DS 1 V f I V = V V V stat f OL x f V x R T DS 2 Vx=0 no power used Vx=5v, Ps = Istat Vdd Istat = 0.2mA, Ps = 0.2mA x 5v = 1mW 10,000 inverters => 10W V = 5 V x

Figure 3.50 Dynamic current flow in CMOS circuits V DD V I x D I D V V f f V x Pd = f CVdd^2 C = 70 fF, f = 100 MHz, Pd = 175uW 10,000 inverters and 20percent switch => 0.35mW (a) Current flow when input V (b) Current flow when input V x x changes from 0 V to 5 V changes from 5 V to 0 V Figure 3.50 Dynamic current flow in CMOS circuits

Figure 3.51 Poor use of NMOS and PMOS transistors VA = VDD – VT Body effect increases VT to 1.5 VT VDD=5v VT=1v VOH = 3.5V Figure 3.51 Poor use of NMOS and PMOS transistors

Figure 3.52 Poor implementation of a CMOS AND gate Logic Logic V f Voltage value value V x x V f x 1 2 f 1 1.5 V V 1 1.5 V V DD x 1 1.5 V 2 1 1 3.5 V 1 (a) An AND gate circuit (b) Truth table and voltage levels Figure 3.52 Poor implementation of a CMOS AND gate

Figure 3.53 High fan-in NMOS NAND gate tp = 1.7C / kn’ W/L VDD x k Figure 3.53 High fan-in NMOS NAND gate

Figure 3.54 High fan-in NMOS NOR gate V DD V f V V V x x x 1 2 k Figure 3.54 High fan-in NMOS NOR gate

Figure 3.55 The effect of fan-out on propagation delay 1 V f f To inputs of To inputs of x x n other inverters n other inverters C n (a) Inverter that drives n other inverters (b) Equivalent circuit for timing purposes V for n = 1 f V DD V for n = 4 f Gnd Time (c) Propagation times for different values of n Figure 3.55 The effect of fan-out on propagation delay

Figure 3.56 A noninverting buffer

Figure 3.57 Tri-state buffer = 0 e x f x f e = 1 x f (a) A tri-state buffer (b) Equivalent circuit e x f e Z 1 Z x f 1 1 1 1 (c) Truth table (d) Implementation Figure 3.57 Tri-state buffer

Figure 3.58 Four types of tri-state buffers

Figure 3.59 An application of tri-state buffers x f 1 s x 2 Figure 3.59 An application of tri-state buffers

Figure 3.60 A transmission gate x f Z 1 x s (a) Circuit (b) Truth table s = x f = Z s x f s = 1 x f = x s (c) Equivalent circuit (d) Graphical symbol Figure 3.60 A transmission gate

Figure 3.61 a Exclusive-OR gate = x Å x 1 2 1 2 1 1 x 1 1 1 f = x Å x x 1 2 1 1 2 (a) Truth table (b) Graphical symbol x 1 x 2 f = x Å x 1 2 (c) Sum-of-products implementation Figure 3.61 a Exclusive-OR gate

Figure 3.61 b CMOS Exclusive-OR gate 2 f = x Å x 1 2 (d) CMOS implementation Figure 3.61 b CMOS Exclusive-OR gate

Figure 3.62 A 2-to-1 multiplexer built using transmission gates

(a) Dual-inline package V DD Gnd (b) Structure of 7404 chip Figure 3.21 A 7400-series chip

Figure 3.22 Implementation of f = x1x2 + x2x3 V DD 7404 7408 7432 x 1 x 2 x 3 f Figure 3.22 Implementation of f = x1x2 + x2x3

Figure 3.23 The 74244 buffer chip

Figure 3.24 Programmable logic device as a black box Logic gates Inputs and Outputs (logic variables) programmable (logic functions) switches Figure 3.24 Programmable logic device as a black box

Figure 3.25 General structure of a PLA x x x 1 2 n Input buffers and inverters x x x x 1 1 n n P 1 AND plane OR plane P k f f 1 m Figure 3.25 General structure of a PLA

Figure 3.63 An example of a NOR-NOR PLA 1 2 3 NOR plane V DD V DD V DD S 1 V DD S 2 V DD S 3 NOR plane f f 1 2 Figure 3.63 An example of a NOR-NOR PLA

Figure 3.26 Gate-level diagram of a PLA x x x 1 2 3 Programmable connections OR plane P 1 P 2 P 3 P 4 AND plane Figure 3.26 Gate-level diagram of a PLA f f 1 2

Figure 3.27 Customary schematic of a PLA x x x 1 2 3 OR plane P 1 P 2 P 3 P 4 AND plane f f 1 2 Figure 3.27 Customary schematic of a PLA

(b) A programmable switch x x x 1 2 n V DD = V e S 1 V DD (b) A programmable switch S 2 V e V DD ++++ +++++ S k ++++ + ++++++ ++++ + (c) EEPROM transistor (a) Programmable NOR-plane

Figure 3.65 A programmable version of a NOR-NOR PLA x x x x 1 2 3 4 NOR plane V DD V DD S 1 S 2 S 3 S 4 S 5 S 6 NOR plane f f Figure 3.65 A programmable version of a NOR-NOR PLA 1 2

Figure 3.66 A NOR-NOR PLA used for sum-of-products x x x x 1 2 3 4 NOR plane V DD V DD P 1 P 2 P 3 P 4 P 5 P 6 NOR plane Figure 3.66 A NOR-NOR PLA used for sum-of-products f f 1 2

Figure 3.28 An example of a PAL 1 2 3 P 1 f 1 P 2 P 3 f 2 P 4 AND plane Figure 3.28 An example of a PAL

Figure 3.67 PAL programmed to implement two functions x x x x 1 2 3 4 V DD P 1 P 2 f 1 P 3 P 4 P 5 f 2 P 6 NOR plane Figure 3.67 PAL programmed to implement two functions

Figure 3.29 Output circuitry Select Enable f 1 Flip-flop D Q Clock To AND plane Figure 3.29 Output circuitry

Figure 3.30 A PLD programming unit

Figure 3.31 A PLCC package with socket

Figure 3.32 Structure of a CPLD I/O block PAL-like PAL-like I/O block block block Interconnection wires I/O block PAL-like PAL-like I/O block block block Figure 3.32 Structure of a CPLD

Figure 3.33 A section of a CPLD

Figure 3.34 CPLD packaging and programming

Figure 3.35 Structure of an FPGA Logic block Interconnection switches I/O block I/O block I/O block I/O block Figure 3.35 Structure of an FPGA

Figure 3.36 A two-input lookup table

Figure 3.37 A three-input LUT x 1 x 2 0/1 0/1 0/1 0/1 f 0/1 0/1 0/1 0/1 x 3 Figure 3.37 A three-input LUT

Figure 3.38 Inclusion of a flip-flop with a LUT

Figure 3.39 A section of a programmed FPGA

Figure 3.68 Pass-transistor switches in FPGAs

Figure 3.69 Restoring a high voltage level DD SRAM 1 V B V To logic block A Figure 3.69 Restoring a high voltage level

Custom Chips Created from scratch. Designer selects number, placement, and connections for each and every transistor. Are most dense and highest speed. Requires a substantial design effort. Used only when high performance and density is required: processors/memories.

Standard-Cell Chips Gates prebuilt and stored in a library. Gates needed for a design are selected and placed, and wires are routed between them. Standard-cell chips often called application specific integrated circuits (ASICs). Saves time since gates are reused. CAD tools exist to place and route gates.

Figure 3.40 A section of two rows in a standard-cell chip

Gate-Arrays Parts of chip are prefabricated (transistors). Parts of chip are custom fabricated (wires). Provides cost savings since all template wafers are identical. Many variants exist.

Figure 3.41 A sea-of-gates gate array

Figure 3.42 An example of a logic function in a gate array

Concluding Remarks Introduced basics of using transistors for digital logic. Described several types of IC chips: Standard chips from the 7400 series. Various types of PLDs. Custom and semi-custom chips.

Figure P3.11 Circuit for problem 3.55 V x 1 V x 2 V f Figure P3.11 Circuit for problem 3.55