Virtual NanoFab A Silicon NanoFabrication Trainer

Slides:



Advertisements
Similar presentations
Malaviya National Institute of Technology
Advertisements

FABRICATION PROCESSES
Process Flow : Overhead and Cross Section Views ( Diagrams courtesy of Mr. Bryant Colwill ) Grey=Si, Blue=Silicon Dioxide, Red=Photoresist, Purple= Phosphorus.
CMOS Fabrication EMT 251.
CMOS Process at a Glance
VLSI Design Lecture 2: Basic Fabrication Steps and Layout
NanoFab Simulator Update Nick Reeder, May 31, 2012.
INTEGRATED CIRCUITS Dr. Esam Yosry Lec. #6.
1 Microelectronics Processing Course - J. Salzman - Jan Microelectronics Processing Oxidation.
Overview of Nanofabrication Techniques Experimental Methods Club Monday, July 7, 2014 Evan Miyazono.
Fabrication of p-n junction in Si Silicon wafer [1-0-0] Type: N Dopant: P Resistivity: Ω-cm Thickness: µm.
Week 10a – Introduction to Semiconductors and Diodes
Design and Implementation of VLSI Systems (EN1600) lecture04 Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Sedra/Prentice.
Elettronica D. AA Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process CMOS Manufacturing Process.
1 N/P-Channel MOSFET Fabrication By Assoc. Prof Dr. Uda Hashim School of Microelectronic Enginnering KUKUM FOX N-Well Arsenic Implant LDD As+ S/D Implant.
The Physical Structure (NMOS)
Design and Implementation of VLSI Systems (EN0160) Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Sedra/Prentice Hall, Saint/McGrawHill,
The Deposition Process
YoHan Kim  Thin Film  Layer of material ranging from fractions of nanometer to several micro meters in thickness  Thin Film Process 
ECE 424 – Introduction to VLSI Design Emre Yengel Department of Electrical and Communication Engineering Fall 2012.
Device Fabrication Example
Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process CMOS Manufacturing Process.
NanoFab Trainer Update Nick Reeder, March 14, 2014.
Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-1  10 Micrometer Design Rules  4 Design Layers.
Katedra Experimentálnej Fyziky Bipolar technology - the size of bipolar transistors must be reduced to meet the high-density requirement Figure illustrates.
Top Down Method Etch Processes
INTEGRATED CIRCUITS Dr. Esam Yosry Lec. #7. Etching  Introduction  Etching  Wet Etching  Dry Etching  Plasma Etching  Wet vs. Dry Etching  Physical.
ISAT 436 Micro-/Nanofabrication and Applications MOS Transistor Fabrication David J. Lawrence Spring 2001.
Z. Feng VLSI Design 1.1 VLSI Design MOSFET Zhuo Feng.
Micro-fabrication.
CS/EE 6710 CMOS Processing. N-type Transistor + - i electrons Vds +Vgs S G D.
Fabrication of Active Matrix (STEM) Detectors
NanoFab Trainer Update Nick Reeder, April 5, 2013.
Nano/Micro Electro-Mechanical Systems (N/MEMS) Osama O. Awadelkarim Jefferson Science Fellow and Science Advisor U. S. Department of State & Professor.
1. A clean single crystal silicon (Si) wafer which is doped n-type (ColumnV elements of the periodic table). MOS devices are typically fabricated on a,
SEMINAR ON IC FABRICATION MD.ASLAM ADM NO:05-125,ETC/2008.
I.C. Technology Processing Course Trinity College Dublin.
SEMINAR PRESENTATION ON IC FABRICATION PROCESS
Feb 2007Stith1 Semiconductors Material, Components, and Manufacture Joseph Stith February 2007.
Introduction to CMOS VLSI Design CMOS Fabrication and Layout Harris, 2004 Updated by Li Chen, 2010.
Introduction to Wafer fabrication Process
Top Down Manufacturing
By: Joaquin Gabriels November 24 th,  Overview of CMOS  CMOS Fabrication Process Overview  CMOS Fabrication Process  Problems with Current CMOS.
NanoFab Trainer Nick Reeder June 28, 2012.
Top Down Method Etch Processes
Introduction EE1411 Manufacturing Process. EE1412 What is a Semiconductor? Low resistivity => “conductor” High resistivity => “insulator” Intermediate.
Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 3, slide 1 Introduction to Electronic Circuit Design.
NanoFab Trainer Update Nick Reeder, February 28, 2014.
IC Processing. Initial Steps: Forming an active region Si 3 N 4 is etched away using an F-plasma: Si3dN4 + 12F → 3SiF 4 + 2N 2 Or removed in hot.
ISAT 436 Micro-/Nanofabrication and Applications Photolithography David J. Lawrence Spring 2004.
CORPORATE INSTITUTE OF SCIENCE & TECHNOLOGY, BHOPAL DEPARTMENT OF ELECTRONICS & COMMUNICATIONS NMOS FABRICATION PROCESS - PROF. RAKESH K. JHA.
NanoFab Simulator Update Nick Reeder, May 17, 2012.
Substitute beer and pizza?. Basic Silicon Solar Cell as fabricated in Cameron With Schematic.
©2008 R. Gupta, UCSD COSMOS Summer 2008 Chips and Chip Making Rajesh K. Gupta Computer Science and Engineering University of California, San Diego.
NanoFab Trainer Update Nick Reeder, March 1, 2013.
 Refers to techniques for fabrication of 3D structures on the micrometer scale  Most methods use silicon as substrate material  Some of process involved.
CMOS VLSI Fabrication.
CMOS FABRICATION.
Side ViewTop View Beginning from a silicon wafer.
Patterning - Photolithography
CMOS Fabrication EMT 251.
Lecture 2 State-of-the art of CMOS Technology
IC Manufactured Done by: Engineer Ahmad Haitham.
CMOS Fabrication CMOS transistors are fabricated on silicon wafer
NanoFab Simulator Update
VLSI System Design LEC3.1 CMOS FABRICATION REVIEW
Silicon Wafer cm (5’’- 8’’) mm
Chapter 1.
NanoFab Trainer Update
CSE 87 Fall 2007 Chips and Chip Making
Presentation transcript:

Virtual NanoFab A Silicon NanoFabrication Trainer Nick Reeder, Sinclair Community College Andrew Sarangan, University of Dayton Jamshid Moradmand, Sinclair Community College

Challenge: Providing Hands-on Silicon Nanofabrication Experience The facilities needed to do silicon nanofab are very expensive.

Solution: Virtual Nanofab Software that we’re developing to teach students about the steps involved in processing a silicon wafer. Please take a copy of the installation disc! System Requirements: Operating system: Windows XP or higher Memory: 2 GB RAM Hard drive: 300 MB of free space If your computer does not have National Instruments LabVIEW installed, you must install the free LabVIEW run-time engine, which is included on the installation disc.

Example: Fabricating a MOSFET MOSFET = Metal-oxide-semiconductor field effect transistor

MOSFET in Virtual NanoFab The structure shown required about 25 steps.

User Operations Thermal oxidation Photolithography Removing material Spin coat Mask Expose Develop Removing material Wet etch Dry etch Depositing layers of material E-beam evaporation Chemical Vapor Deposition (CVD) Sputtering Ion implantation (“doping”)

Thermal Oxidation Grows a layer of silicon dioxide (SiO2) on the wafer surface. Key properties of SiO2: Impervious to ion implantation. Can be etched away by immersion in hydrofluoric acid (HF), which does not etch silicon.

Thermal Oxidation in Virtual NanoFab

Photolithography Steps in photolithography: Spin-coat photoresist. Create and place mask. Mask defines which areas will be exposed to UV light and which areas will be shaded. Expose with UV light. “Develop” the photoresist: UV-exposed areas are removed, while shaded areas remain.

Photolithography in Virtual NanoFab Before exposing: After exposing (but before developing): After developing:

Exposure with Uneven Layer Thicknesses Note that resist above silicon is more fully exposed than resist above aluminum.

Removing material Methods of removing material Wet etching Dry etching Low-tech Immerse wafer in a bath of liquid acid or solvent Dry etching High-tech Expose wafer to plasma beam

Etching in Virtual NanoFab SiO2 (blue) after wet etch with hydrofluoric acid: note tapered sidewalls and undercut of photoresist (pink). SiO2 after dry etch with CF4 plasma: note vertical sidewalls.

Depositing Layers Methods of depositing materials Electron-beam evaporation Chemical vapor deposition (CVD) Sputtering

Deposition in Virtual NanoFab Evaporated titanium (gray): accumulates only on horizontal surfaces. Chemical-vapor-deposited titanium: adheres to vertical surfaces as well as horizontal.

Ion Implantation Modifies the electrical characteristics of the silicon wafer: key to the operation of semiconductor devices such as diodes and transistors. Implanting boron results in “p-type” doping. Implanting phosphorus results in “n-type” doping.

Ion Implantation in Virtual NanoFab

Other Features Maintains history of user operations. “Reference & Videos” page provides chapters explaining theory, along with videos of operations being performed in the lab.