Radiation Effects Digital Tester: Why is this needed? Kenneth A. LaBel Co-Manager, NASA Electronic Parts and Packaging (NEPP) Program

K. LaBel - Need for New Radiation Effects Tester – Feb 18, Outline Test Sources and Constraints Three testers: each has a niche –High-speed technologies –High-speed “CMOS” generic –“Cheap” tester Charts from June 2004 Kickoff

K. LaBel - Need for New Radiation Effects Tester – Feb 18, Typical Ground Sources for Space Radiation Effects Testing Issue: TID - –Co-60 (gamma), X-rays, Proton Issue: Displacement Damage – –Proton, neutron, electron (solar cells) SEE (GCR) –Heavy ions, Cf SEE (Protons) –Protons (E>10 MeV) SEE (atmospheric) –Neutrons, protons Wide Field Camera 3 E2V 2k x 4k n-CCD in front of Proton Beam at UCDavis

K. LaBel - Need for New Radiation Effects Tester – Feb 18, Radiation Test Facilities Used BY NASA/GSFC Co-60 –Source at GSFC X-Ray –NAVSEA Crane Heavy Ion –Texas A&M –Brookhaven National Labs –Lawrence Berkeley National Labs –MSU National Superconducting Cyclotron Lab (NSCL) Proton (SEE) –U. of California at Davis –Indiana University Cyclotron Facility –Mass. General Proton Damage (Materials) –Van de Graaff at GSFC

K. LaBel - Need for New Radiation Effects Tester – Feb 18, Why is a new tester needed? Changes in technology –Speed and packaging Custom hardware for packaging High speed impacts cabling, thermal, power,… ESD Transients Facilities –Remote chamber (air or vacuum) –Activation potential (proton irradiation) –Secondaries from protons We’ve had secondary neutrons cause failures in “nearby” test equipment Portability –Rugged Cost –Modern ATE/BERT systems run to the millions and are not very portable BERTs are VERY sensitive to shipping: we have had more issues with non-functioning equipment

K. LaBel - Need for New Radiation Effects Tester – Feb 18, Philosophy: Three Types of Testers Ultra-fast for SiGe, InP, etc… –Circuit for Radiation Effects Self-Test (CREST)/Built-in Error Self-Test (BEST) Collaborative effort with DTRA, Mayo, OGA, etc Speed test limited to technology of ICs (current IBM 5hp – 8 GHz, 8hp should be approaching 20 GHz) Test chips need to be 128-bit shift registers –Can be used for Boeing/Georgia Tech SiGe test structures High-speed for CMOS –Needed for generic high-speed test devices (> 500 MHz I/O) Processors, FPGAs, etc… –Problem: Cost per copy (~$20K RE) – if we do proton test, board gets activation/dose and must “cool down” before can be shipped –May also fail due to exposure Low-speed (cheap) –At ~ $2-3K per copy, essentially throwaway Moderate speed (few hundred MHz)

K. LaBel - Need for New Radiation Effects Tester – Feb 18, Test Support – CMOS Technology CREST/BERT Methodology is adequate when specific shift- register based test structures are available –What do you do when “other” structures are available for evaluation? Existing “off-the-shelf” test systems are either –Non-portable ($M ATE) or –Designed for a few 100 MHz maximum operation Scaled CMOS can operate at much higher internal clock speeds (look at >3GHz Pentiums!) –Recent data on CMOS (Benedetto, et al) has shown what the SiGe/GaAs test world has known Higher clock speeds vastly complicate error modes from single particle strikes and test fixturing –Even worse when technology speed limit is pushed Question: how do you build a tester that is “Generic” and approach at-speed data collection? From June 2004 RHBD Kickoff Meeting

K. LaBel - Need for New Radiation Effects Tester – Feb 18, “New” Test System Concept Test system focuses on digital SEE/functionality test –Flexible architecture to accommodate unknown test structures (memory, ALU, ring oscillator, etc.) –Portable –Must be able to decipher SEUs from SETs (at least 1 st order) Means at-speed testing with variable input clock –Implies local (on-board) data capture) Temperature, power, etc other usual constraints Concept –Use the power of state-of-the-art reprogrammable FPGAs as the tester (processing IP) Build 2 versions –Daughtercard plug-ins (slower devices) –Device under test (DUT) on-board (faster devices) Reprogrammable FPGA device with embedded processor and HS serial link Test chip with unknown test structures – socketed/on-board or daughtercard New Generic Tester Digital I/O and other From June 2004 RHBD Kickoff Meeting

K. LaBel - Need for New Radiation Effects Tester – Feb 18, Test Card Concept DUT or BEST Optional SiPo, Level Translators, Drivers/Receivers, etc. Reprogrammable FPGA High-Speed Clock From June 2004 RHBD Kickoff Meeting