CSE115: Digital Design Lecture 20: Comparators, Adders and Subtractors Faculty of Engineering

Suggested Reading – Sections

MEMORY DATAPATH CONTROL INPUT - OUTPUT RAM, ROM, Registers, … Finite state machine: PLA, Counters, Flip- flops, Latches, … Interconnect: Switches, Arbiters, Bus, … Arithmetic Unit: Adder, Multiplier, Shifter, Comparator, … Building Blocks for Digital Architectures CPU A Generic Digital Processor

Bit-Sliced Design Bit 3 Bit 2 Bit 1 Bit 0 Control Tile identical processing elements Register Adder Shifter Multiplexer DATA-IN DATA-OUT

Comparators Compares Two binary words and indicate if they are equal A Comparator ComparatorA=B B A>B A>B A<B A<B A B F Advanced Comparators: 1-bit Comparator: XOR gate, the Output is 1 if A  B A Comparator Comparator B A=B

Equality Comparators 4-bit comparator EQ_L 1-bit comparator

Iterative Comparator EQIXYEQO 0XX XY EQI EQI EQO EQO 1 bit comparator:

Multibit Iterative Comparator EQ0 =1 X0 X0 Y0 Y0 X1 X1 Y1 Y1 X(N-1) X(N-1) Y(N-1) Y(N-1)EQN X Y EQI EQI EQO EQO EQ1 EQ1 X Y EQI EQI EQO EQO EQ1 EQ1 X Y EQI EQI EQO EQO EQ1(N-1) Iterative Comparator: cascaded 1 bit comparators

MSI Comparator: 74x85B0 A1 B1 A2 B2 A3 A0 B3 74x85 74x85A<BIN A=BIN A>BIN A<BOUT A=B OUT A>BOUT 4 bit comparator (A<B)+(A=B).(A<B IN) (A>B)+(A=B).(A>B IN) (A=B).(A=B IN) 3 Cascading inputs Cascading inputs initial values: (A=B IN) = 1 (A>B IN) = 0 (A<B IN) = 0

8 bit ComparatorB0 A1 B1 A2 B2 A3 A0 B3 74x85 74x85A<BIN A=BIN A>BIN A<BOUT A=B OUT A>BOUT B0 A1 B1 A2 B2 A3 A0 B3 74x85 74x85A<BIN A=BIN A>BIN A<BOUT A=B OUT A>BOUT B0 A1 B1 A2 B2 A3A0B3 B4 A5 B5 A6 B6 A7A4B7 +5V A<BA=B A>B Most Significant bits Least Significant bits

Half Adder XYSUMC OUT SUM = X  Y C OUT = X.Y Y X S C OUT

Full Adder 1-bit-wide adder, produces sum and carry outputs XYCinSCout S = X’Y’C IN +X’YC IN ’+XY’C IN ’+XYC IN S = X  Y  C IN C OUT = XY + XC IN + YC IN

Full-Adder Circuit S = X  Y  C IN C OUT = XY + XC IN + YC IN

Ripple Adder Speed limited by carry chain: t adder  (n-1)t carry + t sum Goal: Make the fastest possible carry path circuit Faster adders eliminate or limit carry chain  2-level AND-OR logic  2 n product terms  3 or 4 levels of logic, carry lookahead Cascade n Full Adders to get n-bit binary Adder

Subtraction is the same as addition of the two’s complement. The two’s complement is the bit-by-bit complement plus 1. X – Y = X + Y’ + 1 Complement Y inputs to adder, set C in to 1. For a borrow, set C in to 0. XY’ 1 Subtraction

Full Subtractor ≈ Full adder

M = 0: Ripple Adder M = 1: Ripple Subtractor X0 X0 Y0 Y0 X1 X1 Y1 Y1 X(n-1) X(n-1) Y(n-1) Y(n-1) COUT/ BOUT S0/D0 S0/D0 S(n-1) / D(n-1) S(n-1) / D(n-1) S1/D1 S1/D1 X Y COUT COUT CIN CIN S X Y COUT COUT CIN CIN S X Y COUT COUT CIN CIN S M Adder/Subtractor Circuit

CLL: Carry Lookahead Logic X Y CLL CLL S X Y S S0 S0 S1 S1S(n-1) X0 X0 Y0 Y0 X1 X1 Y1 Y1 X(n-1) X(n-1) Y(n-1) Y(n-1)I(n-1)I1I0 Carry Lookahead Adder Units CLL CLL X Y S COUT Carry Lookahead Adder

S Yi Yi Xi Xi Ci Ci S Ci+1 Ci+1 Yi Yi Xi XiXi-1 X0 Yi-1 Y0 C0 Ci Ci Carry Lookahead Logic hsi hsi Adder Full Adder vs. Carry Lookahead Adder

We need to provide an expression for the c i in the CLL Unit When does the Full adder produce carry? Answer: If both X i and Y i equal 1 (carry is generated) OR.. If C i =1 and either X i or Y i equal 1 (carry is propagated)  C i+1 = (X i.Y i ) + (X i +Y i ).C i {Compare to: C OUT =XY + XC IN + YC IN } C i+1 = g i + p i.C i Let g i = X i.Y i p i = X i + Y i Generate Propagate Carry Lookahead Logic

C 1 = g 0 + p 0.C 0 C 2 =g 1 + p 1.C 1 = g 1 + p 1 g 0 + p 1.p 0.C 0 C 3 = g 2 + p 2.C 2 = g 2 + p 2.g 1 + p 2.p 1.g 0 + p 2.p 1.p 0.C 0 C 4 = g 3 + p 3.C 3 = g 3 + p 3.g 2 + p 3.p 2.g 1 + p 3.p 2.p 1.g 0 + p 2.p 1.p 0.C 0 C 5 = …………………………………………………………………………………………… C i+1 = g i + p i.C i g i = X i. Y i p i = X i + Y i X0,Y0X1,Y1XN-1,YN-1... C i,0 P 0 C i,1 P 1 C i,N-1 P N-1... Almost the same amount of delay Carry Lookahead Logic

A0 B0 A1 S1 S2 B1 A2 B2 C0 S0 A374x283S3 C4 B3 Uses Carry Lookahead internally 74x283 4-bit Adder

Ripple carry between groups

Lookahead carry between groups

ALU performs Arithmetic and Logical Functions A, B: 4 bit inputs S3, S2, S1, S0: Function select M = 0: Arithmetic operations: + = Plus, – = Minus M = 1: Logical operations: + = OR,. = AND S1 S2 S3 F1 F2 M CIN A0 S0 F0 B074x181F3 COUT A1 B1 A2 B2 A3 B3 A=B A=B P G InputsFunctions S3S2S1S0M=0 (arithmetic)M=1 (logic) 0000A – 1 + CINA’ 0110A – B – 1 + CINA XOR B’ 1001A + B + CINA XOR B 1011(A OR B) + CINA + B 1100A + A + CIN A + CINA MSI Arithmetic Logic Units (ALU )