The Continued Evolution of Re-Configurable FPGAs for Aerospace and Defense Strategic Applications Howard Bogrow

Bogrow 2MAPLD 2005/176 Abstract Present and future aerospace and defense applications continue to demand ever increasing performance, density, and above all flexibility from FPGAs. The Virtex families of re-configurable FPGAs provide the technology to meet these demands. Various members of these families are currently available in both COTs and SMD formats, as well as in radiation tolerant versions. Xilinx is also fully supporting a recently announced software tool that automates the implementation of TMR (Triple Modular Redundancy) into members of these FPGA families for mission critical applications. Xilinx has received government funding towards the development of a Single Event Immune Re-configurable FPGA (SIRF) with possibly strategic performance. This paper will focus on Xilinx currently available Virtex solutions, while also discussing Xilinx's future development efforts. There will also be some discussion of the various manufacturing flows utilized by Xilinx to address the stringent requirements of current and future space missions, as well as the latest package developments.

Bogrow 3MAPLD 2005/ Xilinx Long-Term Commitment to Aerospace & Defense Source: Company reports Xilinx Founded Introduced 1 st field programmable gate array (FPGA) 1 st device qualified to MIL-STD st Standard Military Drawing (SMD) released ISO 9002 certification 1 st 0.35 & 0.25  m FPGAs QML & ISO9001 certifications Virtex million-gate FPGAs 1 st rad tolerant devices 1 st 150nm Virtex-II Platform FPGA Rad tolerant Virtex & SPROMs 1 st 130nm Virtex-II Pro SEE Consortium formed 1 st 90nm Virtex-4 Platform FPGA Rad tolerant Virtex-II Pro Xilinx on Mars

Bogrow 4MAPLD 2005/ nm 90 nm 130 nm 150 nm 180 nm 45 nm year Technology Leadership 1 year Technology Leadership First to 90 nm First to 300 mm SIA Roadmap Xilinx Technology Roadmap Leading SIA Roadmap – 150nm, 130nm and 90nm – 300mm wafers starting with Virtex-II and Virtex-E First 90nm Spartan-3 family in full production First Virtex-4 devices now shipping Virtex-E Extended Memory Virtex-II Virtex-IIPRO Spartan-3 Virtex-4

Bogrow 5MAPLD 2005/176 Aerospace and Defense Virtex Mil Spec Products nm 180nm 150nm 130nm 90nm 65nm Mil-Temp Space Grades Rad Tolerant Next Generation Mil-Temp Space Grades “Rad by Design” Program Mil-Temp Space Grades Virtex-II Virtex-IIPRO Virtex-4

Bogrow 6MAPLD 2005/176 Aerospace and Defense Qualifications Closing the Gap with Commercial Years from Commercial Production Qualification 4 XC3000 XQ4000XL XC4000 XC4000E XQ4000EX XQ4000XL Virtex Virtex-E Virtex-II Virtex-II Pro Space Qualification Military Qualification Program Goals FPGA Family Generations Virtex-4 RadHard By Design Program Virtex-E

Bogrow 7MAPLD 2005/176 Virtex-4 ASMBL™ Columnar Architecture Virtex 4 th Generation advanced FPGA architecture Enables “dial-In” resource allocation mix – Logic, DSP, BRAM, I/O, MGT, DCM, PowerPC Enabled by Flip-Chip packaging technology – I/O columns distributed throughout the device

Bogrow 8MAPLD 2005/176 Three Virtex-4 Platforms Resource K LCs Logic Memory DCMs DSP Slices SelectIO RocketIO PowerPC Ethernet MAC LXFX SX 0.9-6Mb K LCs Mb K LCs Mb Channels 1 or 2 Cores 2 or 4 Cores N/A Density Processor Cores DSP

Bogrow 9MAPLD 2005/176 Process Technology Advances Advanced 90-nm process 11-Layer metallization – 10 copper + 1 aluminum New Triple-Oxide Structures – Lower quiescent power consumption Benefits: – Best cost – Highest performance – Lowest power – Highest density Over 1 million 90 nm FPGAs shipped Channel Gate SourceDrain SourceMetalConnection DrainMetalConnection

Bogrow 10MAPLD 2005/176 Dramatic Power Reduction in Virtex-4 Frequency Power Consumption 50% 130 nm FPGAs Virtex-4 cuts power by 50% Measured 40% lower static power with Triple-Oxide technology 50% lower dynamic power with 90-nm Lower core voltage Less capacitance Up to 10x lower dynamic power with hard IP Integration means fewer transistors per function Challenges - Static power grows with process generations - Transistor leakage current - Dynamic power grows with frequency - P = cv 2 fChallenges - Static power grows with process generations - Transistor leakage current - Dynamic power grows with frequency - P = cv 2 f

Bogrow 11MAPLD 2005/176 Virtex-4 Configuration Features Higher configuration speed – 100MHz Serial & Parallel interface – 66MHz JTAG interface CCLK available to users 256 bit AES security Configuration ECC ICAP and DRP support Dedicated configuration I/O bank Enhanced partial reconfiguration Compatible with previous FPGAs Supports earlier configuration modes CCLK DIN CS_B RDWR_B PROG_B TCK TDI TMS TDO D[7:0] DOUT_BUS Y DONE INIT MODE[2:0]

Bogrow 12MAPLD 2005/176 FPGA Radiation Tolerance TID Trends vs Product/Technology Process trends*: Gate oxide continues to thin Oxide tunnel currents increase Gate stress voltage decreases *See “CMOS SCALING, DESIGN PRINCIPLES and HARDENING-BY- DESIGN METHODOLOGIES” by Ron Lacoe, Aerospace Corp 2003 IEEE NSREC Short Course nm - XQ4000XL – 60 krad (Si) 220nm - XQVR (Virtex ) – 100 krad (Si) 150nm - XQR2V (Virtex-II) – 200 krad (Si) 130nm – XQR2VP – 250 krad (Si) 90nm (Preliminary) – 300 krad (Si)

Bogrow 13MAPLD 2005/176 SEE Consortium Platform FPGA Test Phases Static (1Q05) Dynamic (2Q05) Mitigation (3Q05) V-2pro Multi-Gigabit Serial Transceivers PowerPC Processor & IP FPGA Fabric and Static Cells Parallel Test Approach to accelerate product qualification 3 SEE Consortium Tiger Teams: Fabric, Processor, Serial Transceiver Special Solutions V-2pro V-4

Bogrow 14MAPLD 2005/176 Dose Rate Testing Historical Testing – XC4036XL Testing was done by Lockheed Testing range of 1.0E7 to 4.0E11 (20 nsec pulse) tested No data upset >1.3E9 to >3.0E9 No latch-up beyond 4.0E11 – XCVR300E Testing done by ITT (MRC) Testing range of 6.3E7 to 3.0E9 No upset until > 4.0E8 (non-epi) to >1.0E9 (epi) No latch-up beyond 3.0E9 Current Test Program – XC2VP40 Work is funded by MDA Testing is being done by a consortium consisting of AFRL, Crane, Xilinx and Raytheon Initial tests were run July 2004 at Navsea Crane using 60 MeV electron beam source utilized commercial Virtex-IIpro performance board and commercial V-IIpro parts Tests to compare RH (epi) performed in November 2004 at Navsea Crane No upset until > 3.0E8 RH (epi) no POR until >1.0E9 No Latch-up through >1.0E10

Bogrow 15MAPLD 2005/176 Software development tool to automatically implement TMR customer designs optimized for Xilinx FPGAs Result of Xilinx/Sandia National Labs partnership – Released to Production in Sept 2004 Support all design entry methods and HLLs – NGO & NGC based input – EDIF based output OS Support – Windows 2000/XP GUI Support – Windows/UNIX PERL Command Line Support Supports ISE 5.2i, 6.1i, 6.2i TMRTool

Bogrow 16MAPLD 2005/176 Xilinx Design Flow TMRTool Netlist Flow

Bogrow 17MAPLD 2005/176 RocketIO™ Multi-Gigabit Transceiver Block Memory Clocking & Clock Mgmt PowerPC™ Configuration Memory Control Logic Logic Fabric DSP Fabric Virtex-4 Silicon Floorplan SelectIO Phase-1: Design Feasibility, Test Chip Phase-2: Chip Development Phase-2A: Advanced Features RadHard by Design Program SEU Immune Reconfigurable FPGA (SIRF)

Bogrow 18MAPLD 2005/176 SIRF Radiation Goals

Bogrow 19MAPLD 2005/176 CG717 o 35 x 35mm body, 1.27mm pitch, cavity-up o Footprint compatible with the BG728BG728 o Developed for the 2V3000 o Wire Bond, gold o Au-Sn lid (hermetically sealed) CF1144 o 35 x 35mm body, 1.00mm pitch o Footprint compatible with the FF1152FF1152 o Developed for the 2V6000 o Flipchip with high lead balls, MSL1 Advanced Packaging

Bogrow 20MAPLD 2005/176 Enhanced Flow – In Development

Bogrow 21MAPLD 2005/176 Summary Virtex-4 architecture and design methodology enables rapid development of Platform-specific FPGAs with embedded cores Advances in 90nm chip design resulted in optimized performance, lower power, and first-silicon success of Virtex-4 SEE Consortium primary vehicle for radiation characterization testing (US and European) Rad Tolerant program will continue with concurrent phase-in of Rad Hard by Design program Advanced packaging and enhanced process flows integral part of overall development efforts