Computer Organization and Design Computer Abstractions and Technology CEN 316 Computer Architecture for Computer Science Dr. Mansour Al Zuair References: www.cs.berkeley.edu/~patterson Dr. Hisham Al Twaijry presentations www.cs.berkeley.edu/~lazzaro Greet class

Class Objectives You want to call yourself a “computer scientist” You need to make a purchasing decision or offer “expert” advice? Understand the interface between the software and hardware. The basis of understanding the program performance design the system software (compiler, OS) for a new processor To learn the factors affecting the performance of a program and how to improve the performance choose right computers for a set of applications in a project. interpret the benchmark figures given by salespersons. Write efficient programs To learn the principles for designing processors and systems and To learn the system configuration trade-off techniques to improve the performance of hardware

Class Objectives Understand assembly-language programming Write assembler-language programs for MIPS Know how programs translate to machine language Learn system functional partition and interfaces Processor, memory, input/output Understand performance assessment & components Interpret measures and avoid common flaws Know how system characteristics affect performance Understand basic computer arithmetic Understand how computer “executes” instructions Understand basics of modern memory and I/O systems

Computer architecture forces and trends Today’s Lecture Computer architecture forces and trends Technology Semiconductor Magnetic storage System price/performance 1965..today Future Define Computer Architecture Levels of abstraction Computer system organization

Computer Architecture Instruction Set Architecture + Machine Organization Instruction set What does the machine understand? What does the machine need to understand? What is the interface between hardware and software? Machine organization How does it work? How do we design a computer? How does the speed depend on the design?

Anatomy: 5 components of any Computer Personal Computer Keyboard, Mouse Computer Processor Memory (where programs, data live when running) Devices Disk (where programs, data live when not running) Control (“brain”) Input Datapath (“brawn”) Output That is, any computer, no matter how primitive or advance, can be divided into five parts: 1. The input devices bring the data from the outside world into the computer. 2. These data are kept in the computer’s memory until ... 3. The datapath request and process them. 4. The operation of the datapath is controlled by the computer’s controller. All the work done by the computer will NOT do us any good unless we can get the data back to the outside world. 5. Getting the data back to the outside world is the job of the output devices. The most COMMON way to connect these 5 components together is to use a network of busses. Display, Printer

Computer Technology - Dramatic Change! Processor 2X in speed every 1.5 years (since ‘85); 100X performance in last decade. Memory DRAM capacity: 2x / 2 years (since ‘96); 64x size improvement in last decade. Disk Capacity: 2X / 1 year (since ‘97) 250X size in last decade.

Tech. Trends: Microprocessor Complexity 2X transistors/Chip Every 1.5 to 2.0 years Called “Moore’s Law”

Technology Trends: Memory Capacity (Single-Chip DRAM) Now 1.4X/yr, or 2X every 2 years.

Moore’s Law Transistors Per Die Pentium™ Processor 8080 8086 80286 Intel386™ Intel486™ 2000 1970 1975 1980 1985 1990 1995 4004 108 107 106 105 104 103 102 101 1 16M 1K 4K 16K 64K 256K 1M 4M Moore’s Law: No. Transistors per chip increases 4 every 3 years CAGR = 60%

Workstation Performance Improving 54% per year Performance Growth H P 9 / 7 5 S U N - 4 2 6 M I 1 B R 3 8 D E C A l p h a X O W Y e r f o m n c Workstation Performance Improving 54% per year

System Price/Performance 1977 1965 2005 IBM System 360/50 0.15 MIPS 64 KB $1M $6.6M per MIPS DEC VAX11/780 1 MIPS 1 MB $200K $200K per MIPS Intel Xeon Dual core 3 GH More than 18000 MIPS $2000 $.11 per MIPS

Types of computers

Types of microprocessors

Program Performance Where is this topic covered How this component affect performance HW or SW component Not this course Determine both the number of source-level statements and the number of IO operations executed Algorithm Chapter 2 and 3 Determine the number of machine instructions for each source level statement Programming language, compiler and architecture Chapters 5,6, and 7 Determine how fast instructions can be executed Processor and memory system Chapter 8 Determine how fast I/O operations may be executed I/O system

Below your Program

Where is “Computer Architecture and Engineering”? I/O system Processor Compiler Operating System (Windows 2K) Application (Netscape) Digital Design Circuit Design Instruction Set Architecture Datapath & Control transistors Memory Hardware Software Assembler Coordination of many levels of abstraction

Key Concepts of Abstraction Instruction Set Architecture (ISA) Functional interface for assembly-language programmer Examples: MIPS, SPARC, PowerPC, HP PA, Alpha, Intel (x86), IBM System/390, IBM AS/400 Implementation (Machine Organization) Partitioning into units and logic design Examples Intel386 CPU, Intel486 CPU, Pentium® Processor, Pentium® II Processor, .. Alpha 21064, 21164, 21264

Key Concepts of Abstraction Realization Physical fabrication and assembly Examples IBM 703(?) built with vacuum tubes and 7090(?) built with transistors Pentium Processor in 0.8 mm, 0.6mm, 0.35 mm BiCMOS/CMOS

Forces on Computer Architecture Technology Programming Languages Operating systems History Applications Organizational techniques

Instruction Set Architecture “... Consists of: Organization of storage Data types Encoding and representations (instruction formats) Instruction (or Operation Code) Set Modes for addressing data Items and instructions Program visible exceptional conditions Specifies requirements for binary compatibility across implementations

MIPS I Instruction Set Architecture Instruction Categories Load/Store Computational Jump and Branch Floating Point coprocessor Memory Management Special Three instruction Formats R0 - R31 PC HI LO OP rs rt rd sa funct immediate jump target

Execution Cycle Obtain instruction from program storage Fetch Decode Operand Execute Result Store Next Obtain instruction from program storage Determine required actions and instruction size Locate and obtain operand data Compute result value or status Deposit results in storage for later use Determine successor instruction Conceptual Sequence: Programmer’s view of single instruction execution ISAs generally adopt with limited, specified exceptions

Machine Organization Capabilities & performance of functional units (FUs) registers, ALU Ways in which these components are interconnected nature of information flows between components Choreography of FUs to realize the ISA Register Transfer Level Description Also called microarchitecture or design architecture Logic Designer's View ISA Level FUs, control units, interconnect