DESIGN OF LOW POWER CURRENT-MODE FLASH ADC

Slides:



Advertisements
Similar presentations
1 A Low Power CMOS Low Noise Amplifier for Ultra-wideband Wireless Applications 指導教授 : 林志明 學生 : 黃世一
Advertisements

Analog to Digital Conversion. Introduction  An analog-to-digital converter (ADC, A/D, or A to D) is a device that converts continuous signals to discrete.
DIGITALLY ASSISTED ANALOG CIRCUITS PRESENTATION By Sohaib Saadat Afridi MS (EE) SEECS NUST 1.
PRESENTATION#1. Introduction Motivation Key Research Labs Future Goals Applications Published Research Conclusion.
Quasi-Passive Cyclic DAC Gabor C. Temes School of EECS Oregon State University.
Design and Implementation a 8 bits Pipeline Analog to Digital Converter in The Technology 0.6 μm CMOS Process Eri Prasetyo.
Current-Mode Multi-Channel Integrating ADC Electrical Engineering and Computer Science Advisor: Dr. Benjamin J. Blalock Neena Nambiar 16 st April 2009.
1 A New Successive Approximation Architecture for Low-Power Low-Cost A/D Converter IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.38, NO.1, JANUARY 2003 Chi-sheng.
EET260: A/D and D/A converters
1 Alireza Mahmoodi and Dileepan Joseph University of Alberta, Canada Optimization of Delta-Sigma ADC.
Analog-to-Digital Converters Prepared by: Mohammed Al-Ghamdi, Mohammed Al-Alawi,
CMOS VLSIAnalog DesignSlide 1 CMOS VLSI Analog Design.
A CMOS Low Power Current-Mode Polyphase Filter By Hussain Alzaher & Noman Tasadduq King Fahd University of Petroleum & Minerals KFUPM, Department of Electrical.
High-speed Current- based Comparators ECE 1352 Presentation By: Duy Nguyen.
A Low-Power 4-b 2.5 Gsample/s Pipelined Flash Analog-to-Digital Converter Using Differential Comparator and DCVSPG Encoder Shailesh Radhakrishnan, Mingzhen.
Rail-to-rail low-power high-slew-rate CMOS analogue buffer
A Dynamic GHz-Band Switching Technique for RF CMOS VCO
A 0.35μm CMOS Comparator Circuit For High-Speed ADC Applications Samad Sheikhaei, Shahriar Mirabbasi, and Andre Ivanov Department of Electrical and Computer.
1 A 0.6V ULTRA LOW VOLTAGE OPERATIONAL AMPLIFIER 指導教授:林志明 所長 指導學生:賴信吉 : 彰師大 積體電路設計研究所.
Introduction to Adaptive Digital Filters Algorithms
1 A Low-Voltage Folded- Switching Mixer in 0.18-um CMOS Vojkan Vidojkovic, Johan van der Tang, Member, IEEE, Arjan Leeuwenburgh, andArthur H. M. van Roermund,
1 CMOS Temperature Sensor with Ring Oscillator for Mobile DRAM Self-refresh Control IEEE International Symposium on Circuits and Systems, Chan-Kyung.
1 姓名 : 李國彰 指導教授 : 林志明老師 A 1v 2.4GHz CMOS POWER AMPLIFIER WITH INTEGRATED DIODE LINEARIZER ( The 2004 IEEE Asia-Pacific Conference on Circuits and Systems,
Design of a GHz Low-Voltage, Low-Power CMOS Low-Noise Amplifier for Ultra-wideband Receivers Microwave Conference Proceedings, APMC 2005.
A 12-bit, 300 MS CMOS DAC for high-speed system applications
Guohe Yin, U-Fat Chio, He-Gong Wei, Sai-Weng Sin,
SIGMA-DELTA ADC SD16_A Sigma-Delta ADC Shruthi Sujendra.
Improvement of Accuracy in Pipelined ADC by methods of Calibration Techniques Presented by : Daniel Chung Course : ECE1352F Professor : Khoman Phang.
Design of a 10 Bit TSMC 0.25μm CMOS Digital to Analog Converter Proceedings of the Sixth International Symposium on Quality Electronic Design IEEE, 2005.
CSE 598A Project Proposal James Yockey
A 90nm CMOS Low Noise Amplifier Using Noise Neutralizing for GHz UWB System 指導教授:林志明 教授 級別:碩二 學生:張家瑋 Chao-Shiun Wang; Chorng-Kuang Wang; Solid-State.
1 A CMOS 5-GHz Micro-Power LNA 指導教授 : 林志明 教授 學生 : 黃世一 Hsieh-Hung Hsieh and Liang-Hung Lu Department of Electrical Engineering and Graduate Institute of.
指導教授:林志明 老師 研究生:林高慶 學號:s
A Single Capacitor Bootstrapped Power Efficient CMOS Driver José C. García, Juan A. Montiel–Nelson Institute for Applied Microelectronics, Department of.
A 14-b 100-MS/s Pipelined ADC With a Merged SHA and First MDAC Byung-Geun Lee, Member, IEEE, Byung-Moo Min, Senior Member, IEEE, Gabriele Manganaro, Senior.
IEEE Transactions on Circuits and Systems II: Express Briefs
FE8113 ”High Speed Data Converters”. Part 2: Digital background calibration.
A 1-V 2.4-GHz Low-Power Fractional-N Frequency Synthesizer with Sigma-Delta Modulator Controller 指導教授 : 林志明 教授 學生 : 黃世一 Shuenn-Yuh Lee; Chung-Han Cheng;
1 Successive Approximation Analog-to- Digital Conversion at Video Rates 指導教授 :汪輝明 學 生:陳柏宏.
1 The source drivers for the portable small-scale TFT-LCD 指導教授 : 林志明 學生 : 黃世一
1 Ultra-broadband 20.5 – 31 GHz monolithically-integrated CMOS power amplifier 指導教授 : 林志明 教授 學 生 : 劉彥均 A. Vasylyev, P. Weger and W. Simbu¨rger, ELECTRONICS.
A Tail Current-Shaping Technique to Reduce Phase Noise in LC VCOs 指導教授 : 林志明 教授 學 生 : 劉彥均 IEEE 2005CUSTOM INTEGRATED CIRCUITS CONFERENCE Babak Soltanian.
Adviser : Hwi-Ming Wang Student : Wei-Guo Zhang Date : 2009/7/14
Implantable RF Power Converter for Small Animal In Vivo Biological Monitoring 指導教授:林志明 教授 級別:碩一 學生:張家瑋 Proceedings of the 2005 IEEE Engineering in Medicine.
New Power Saving Design Method for CMOS Flash ADC Institute of Computer, Communication and Control, Circuits and Systems, July 2004 IEEE 班級 :積體碩一 姓名 :黃順和.
A Linearized Cascode CMOS Power Amplifier 指導教授:林志明 老師 研究生:林高慶 學號: Ko, Sangwon; Lin, Jenshan; Wireless and Microwave Technology Conference, 2006.
A HIGH-SPEED LOW-POWER RAIL-TO-RAIL BUFFER AMPLIFIER FOR LCD APPLICATION C-W Lu; Xiao, P.H.; Electrical and Computer Engineering, Canadian Conference on.
1 A 69-mW 10-bit 80-MSample/s Pipelined CMOS ADC 班級 : 積體所碩一 學生 : 林義傑 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 12, DECEMBER 2003.
A 10b Ternary SAR (TSAR) ADC with Decision Time Quantization Based Redundancy Jon Guerber, Manideep Gande, Hariprasath Venkatram, Allen Waters, Un-Ku Moon.
High Speed Analog to Digital Converter
1 A Cost-Efficient High-Speed 12- bit Pipeline ADC in 0.18-m Digital CMOS Terje Nortvedt Andersen, Bj ø rnar Hernes, Member, IEEE, Atle Briskemyr, Frode.
學生 : 李國彰 指導教授 : 賴永齡老師 A 1.5V 2.4GHz CMOS Mixer with high linearity ( The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, December 6-9, 2004.
指導老師:林志明 學生:黃政德 系級:積體所研一
An Analysis of THD in Class D Amplifiers
1 A NEW 12-bits 40 MS/s, LOW-POWER, LOW-AREA PELINE ADC FOR VIDEO ANALOG FRONT ENDS 班級 : 積體所碩一 學生 : 林義傑 RCIM, Dept. of Electrical and Computer Engineering.
Pipelined ADC We propose two variants: low power and reliability optimized A. Gumenyuk, V. Shunkov, Y. Bocharov, A. Simakov.
L.Royer – Calice Manchester – Sept A 12-bit cyclic ADC dedicated to the VFE electronics of Si-W Ecal Laurent ROYER, Samuel MANEN LPC Clermont-Ferrand.
Analog to Digital Converters
Low Power, High-Throughput AD Converters
Class Report 林常仁 Low Power Design: System and Algorithm Levels.
Bandgap Reference Voltage SVTH:Đặng Thanh Tiền. Bandgap Reference Voltage  Abstract  Introduction  Circuit of the BGR  Simulation  Conclusion  References.
Low Power, High-Throughput AD Converters
Outline Abstract Introduction Bluetooth receiver architecture
Wei-chih A Low-Voltage Low-Power Sigma-Delta Modulator for Broadband Analog-to-Digital Conversion IEEE Journal Of Solid-state Circuits, Vol. 40, No. 9,
 Sensor (S)–converts arbitary physical quantity into electric signal  Adaptor (A)–provides signal amplification to a required level; expands a dynamic.
Adiabatic Technique for Energy Efficient Logic Circuits Design
R&D activity dedicated to the VFE of the Si-W Ecal
Chapter 10 Figure 07.
Propagation Time Delay
Chapter 10 Figure 07.
Presentation transcript:

DESIGN OF LOW POWER CURRENT-MODE FLASH ADC Bhat, M.S.; Rekha, S.; Jamadagni, H.S TENCON 2004. 2004 IEEE Region 10 Conference 指導教授:易序忠 學生:劉得吉 學號:95662001

OutLine Abstract Introduction Basics of Current-Mirroring Circuit Implementation Concusions References

Abstract For high-speed operation, current mirroring technique with current comparison architecture is used. The optimization procedure is aimed at minimizing static power consumption, and its impact on circuit performance.

Introduction Generally, current mode circuits neither require amplifiers with high voltage gains there by reducing the need for high performance amplifiers nor require high precision resistors or capacitors. The current comparators have high output impedance, which in turn limit the circuit speed. This paper describes current-mirroring technique with optimal device sizing to achieve signal conversion at low power.

Basics of Current-Mirroring

Basic current comparator circuit The drawback of large output resistance is the increased circuit delay.

Current-mode ADC

Circuit Implementation MP0 – MPP:

Modified current comparator In a higher conversion speed at the expense of increased static power consumption.

Power consumption

Concusions The maximum sampling rate is found to be 80Ms/Sec and a dynamic range of 32uA. The circuit operates at 5 volts power supply dissipating an average power of 78mW.

References C.-C. Chen, C.-Y low-power CMOS current-mode cyclic analog-to-digital converters”, IEEE Trans. on circuits and systems – II: Analog and digital signal processing, vol. 45, no. 1, pp. 28-40, Jan. 1998. M. P. Fl converters with current-mode interpolation”, IEEE J. of solid-state circuits, vol. 31, no. 9, pp. 1248-1257, Sept. 1996. D. G. Nairn and C. A. T. Salama, “A ratio-independent algorithmic analog-to-digital converter combining current-mode and dynamic techniques,” IEEE Trans. Circuits and Systems, vol. 37, pp. 319–325, Mar. 1990. D. G. Nairn and C. A. T. Salama, “Current-mod analog-to-digital converters,” IEEE J. Solid-State Circuits, vol. 25, pp. 997–1004, Aug. 1990. S. J. Daubert and D. Vallanco current-mode modulator,” IEEE J. Solid-State Circuits, vol. 27, pp. 821–830, May 1992. D. Macq and P. G. A. Jespers, “A 10-bit pi switched-current A/D converter,” IEEE J. Solid-State Circuits, vol. 29, pp. 967–971, Aug. 1994. R. C. C. Hui and H. C. Luong pipeline ADC using zero-voltage sampling technique”, IEEE International Symposium on circuits and systems, vol. 1, pp. 9-12, 31 May – 3 Jun, 1998.