DESIGN OF LOW POWER CURRENT-MODE FLASH ADC Bhat, M.S.; Rekha, S.; Jamadagni, H.S TENCON 2004. 2004 IEEE Region 10 Conference 指導教授:易序忠 學生:劉得吉 學號:95662001
OutLine Abstract Introduction Basics of Current-Mirroring Circuit Implementation Concusions References
Abstract For high-speed operation, current mirroring technique with current comparison architecture is used. The optimization procedure is aimed at minimizing static power consumption, and its impact on circuit performance.
Introduction Generally, current mode circuits neither require amplifiers with high voltage gains there by reducing the need for high performance amplifiers nor require high precision resistors or capacitors. The current comparators have high output impedance, which in turn limit the circuit speed. This paper describes current-mirroring technique with optimal device sizing to achieve signal conversion at low power.
Basics of Current-Mirroring
Basic current comparator circuit The drawback of large output resistance is the increased circuit delay.
Current-mode ADC
Circuit Implementation MP0 – MPP:
Modified current comparator In a higher conversion speed at the expense of increased static power consumption.
Power consumption
Concusions The maximum sampling rate is found to be 80Ms/Sec and a dynamic range of 32uA. The circuit operates at 5 volts power supply dissipating an average power of 78mW.
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