NIOS II Ethernet Communication Final Presentation By: Gilad Shterenshis Supervisor: Ina Rivkin Winter 2008

Content Background and Project Goals Development Tools NIOS II System Design Flow SOPC System Design Steps Interface Project Milestones

Background and Project Goals Previous project: Implementation of simple calculator with Altera DE2 Board (Cyclone II) Experiencing development tools and design flow VHDL Schematic editor Current project: Create simple calculator in NIOS II processor using Ethernet interface Implement Ethernet interface to the NIOS II w/o OS Create HW environment for NIOS II processor Create small calculator program in C/C++

Development Tools Software: Hardware: Quartus II 8.1 SOPC Builder 8.1 NIOS II IDE 8.1 Aux S/W Ethereal - Ethernet Sniffer Colasoft Packet Builder Hardware: Altera DE2 Board Cyclone II FPGA Fast Ethernet Controller PC

DM9000A ETH Controller Fast Ethernet MAC controller General processor I/F 10/100 PHY AUTO-MDIX

NIOS II System Design Flow SOPC Builder: Define & Generate System Quartus II: HW Development NIOS II IDE: SW Development Integration Sim/HW

NIOS II System Detailed Design Flow SOPC Builder GUI Processor Library Configure Processor Custom Instructions Peripheral Library Select & Configure Peripherals, IP IP Modules Hardware Development Software Development IDE-Managed Flow User-Managed Flow HDL Source Files Testbench Connect Blocks C Header files Custom Library Peripheral Drivers Generate Quartus II Nios II EDS Hardware Configuration File Executable Code Synthesis & Fitter Verification & Debug Compiler, Linker, Debugger JTAG, Serial, or Ethernet User Design Other IP Blocks On-Chip Debug User Code Libraries RTOS Altera FPGA Software Trace Hard Breakpoints SignalTap® II Quartus II GNU Tools Nios II C2H® Compiler

Project Steps Build a simple SOPC system Using On-Chip memory only Small C library (no user input) Calculator with RS-232 UART I/F Using SDRAM memory Running DE2_NET Example Loop back cable Display sent packets Coding calculator S/W Generating Ethernet packets Integration and Debug

UART System Using RS-232 serial interface (or JTAG UART) Simple S/W calculator SDRAM usage

SOPC Major Components LCD JTAG UART UART NIOS II core PIO Ethernet SDRAM Memory TRI-STATE BRIDGE On-Chip Memory FLASH Memory

SOPC Builder

NIOS II Processor Core

System Setup

Packet Sending and Receiving The controller add and remove 4 bytes of checksum The controller filters packets by MAC address If a packet is received, the NIOS gets an interrupt The NIOS read the packet from the controller

S/W Operation Sequence Main Initiate Controller and peripherals Register function for interrupt Main loop - Transmit UDP packets with result embedded If packet received – Initiate controller Function: ethernet_interrupts Receiving packet Check IP (screen multicast messages) Read packet data Build numbers Calculate result (print to terminal)

Using UDP Simple, one packet communicating Point to point No ACK/NAK required

NIOS II Terminal Sending packets: Receiving packets:

Ethernet Sniffer PC Packet:

Ethernet Sniffer NIOS II packet:

Ethernet Packet Builder UDP packets Enable entering math exercise

Improvements GUI / Web browser I/F Screen non related messages Fields for entering arguments and operation Result Field Screen non related messages

Project Milestones Characterization presentation - 7/01/09 Tutorials Tools learning Implementing simple system NIOS II SW - calculator UART RS232 LCD Implementing ETH I/F H/W development S/W coding Integration Final presentation Project summary submission

Thank You!