IFR barrel upgrade: status of LST option Roberto Calabrese Ferrara University 10/18/2002

Outline General Overview  Standard LST  Modified LST for BaBar Issues  Safety  Reliability  Radiation tolerance  Mechanics (detector assembling, location of electronics)  Electronics  Manpower  Cost Status of R&D Schedule

Standard Limited Streamer Tube Coverless version doesn’t have this PVC cover Coverless PST chamber and E-field lines

A survey of large LST systems systemdatesize 1UA1 (upgraded muon system)  0.9cm tubes covered 800m 2 area, first large PST system used in HEP accelerator experiment. 2NUSEX(Mt. Blanc Lab) ,000 tubes (0.9  0.9cm  3.5m), 1,500m 2. 3CHARM II (CERN SPS) ,232 tubes (0.9  0.9cm  3.75m), 5,820m 2. 4LVD (Gran Sasso Lab) ,000 tubes (0.9  0.9cm  6.3m), 7,560m 2. (constructed by SCARF, Houston-Northeastern) 5ALEPH (LEP, CERN) cell profiles (0.9  0.9cm  7m) for barrel, ?? for end caps of hadron calorimeter. 6DELPHI (LEP, CERN)199020,000 tubes for hadron calorimeter. 7OPAL (LEP, CERN) cell, cell, m long for barrel cell, m long for endcap. Total 52,588 cells.

8SLD (SLAC)199010,000 8-cell modules, length varying from 1.9 to 8.6m. Covered 4500m 2. 9ZEUS barrel and rear muon detector (HERA) PST with length varying from 0.7m to 10.2m. Covered 2,000m 2. Noryl instead of PVC for better wire aging and less safety hazard in case of fire. 10MACRO cm  2.7cm  12m big size tubes. 6 supermodules, 5856 tubes/supermodule. 11COMPASS muon wall detector PST tubes 12SMC (Spin Muon experiment at CERN) cell, 4m long chambers. Total 6144 cells. Covered 245m 2. (Constructed by SCARF, Houston-Northeastern) 13WA98 (SPS, CERN)19992 planes, each contains 19 8-cell, 1.2m long chambers. (earlier generation WA80,WA93 used PST too) 14PHENIX muon identifier X0.9cm  0.9cm  (5.2 or 2.5)m tubes.

LST efficiency The intrinsic efficiency of a standard LST tube is about 90%. This is due to dead spaces in the LST tubes. Efficiency is too low for our purposes. Not enough space to put 2 standard layers. Test (Princeton) on the 10-chamber array with HV = 5000V, Ar/C 4 H 10 (25/75) 89.5%90.7%88.5%86.4% 90.2%93.8%91.8%90.5% 86.8%92.1%92.6%90.2%

Possibilities to improve efficiency (given the allowed space) Option 1: single-layer with a large cell (19x17 mm) Readout of x and y coordinates from outside strips

Possibilities to improve efficiency Option 2: double-layer with a small cell (9x8mm) Readout of x coordinate from wire and y coordinate from outside strips

Possibilities to improve efficiency Option 3: modified double-layer with a small cell (9x8mm) Readout of x and y coordinates from outside strips

Efficiency improvement Minimum path length (mm)

Comparison of induced signals in different configurations Single layer Double layers, back to back Single layer with a same thickness wood spacer

Test results Ratio(double/single) = 0.134/0.207 = 65% Ratio(spacer/single) = 0.094/0.207 = 45%

Test with single-layer with a same thickness wooden spacer

What we can say now Double-layer configuration smears position resolution, but this can be better than 0.5 cm We will be able to use existing FEC if we use a preamplifier with a gain 15

Issues Safety Radiation tolerance Reliability Mechanics (detector assembling, location of electronics) Electronics Manpower Cost

Safety Safe gas mixture, like Ar/Iso/CO 2 (2.5/9.5/88) (SLD) Use Noryl instead of PVC: no clorine in the material

Radiation tolerance: PVC vs Noryl From Zeus experience, Noryl tubes have much better radiation resistance  Wire after 100mC/cm, PVC tube  Wire after 100mC/cm, Noryl tube

Radiation tolerance The expected integrated charge until 2010 for the Barrel Inner Layer is about 5mC/cm (J.Va’vra), of the same order as in Zeus, so no radiation problem is expected, but we need to build Noryl tubes.

Reliability Initial mortality  Based on past experience (Zeus, Phenix), can be kept to a reasonable value (few %) with quality control during the production, and burn-in test before installation. Depend (also) on tube length.  Phenix QC procedure (  only about 20 wires (over 56000) dead as initial mortality Long term failure rate  1% in 6 years (Zeus)  Less than 5% in 10 years (LEP experiments)  4%(endcap), up to 11%(barrel) in 10 years in SLD (11% mainly due to mechanical problems during installation)

Mechanics A detailed study of all aspect of mechanics has to be done:  Every chamber must fit in the 22 mm available space  Detector assembly and installation  Location of FE electronics  Routing of cables A working committee has been setup, which includes mechanical engineers from Princeton (Bill Sands, Richard Fernholz) and Ferrara (Vito Carassiti)

Electronics Different options under study, depending on the use of existing FEC Aims:  Use as much of present RPC electronics as possible, allowing for smaller chamber pulse.  Fit all FE electronics in “accessible” location (not behind iron slabs) Cost evaluation for December Coll. Meeting (preliminary estimation for November?)

Front End for the BaBar IFR upgrade: option 1 (Angelo Cotta Ramusino) Each strip is equipped with a front end preamplifier realized with Components-Off-The-Shelf (COTS). The preamplifiers will have fixed gain. The preamplifiers will have differential outputs and will drive the output signals on micro-ribbon twisted pair cables. The differential signals will be handled by COTS-based differential receivers; these may be equipped with a step-programmable gain stage The single ended output from the receiver cards is then fed to the FECs, all relocated into minicrates outside the iron IRON

Front End for the BaBar IFR upgrade: option 2 (Angelo Cotta Ramusino) Each strip is equipped with a front end preamplifier based on one of the various amplifier/discriminator ASICs designed for HEP applications The dynamic of the IFR detector must be matched to the ASIC’s one (by means of a passive network ahead of it) A new programmable module, ICB-like, must provide the threshold voltage for the front end ASIC The ASIC will drive the output signals (LVDS level) on micro-ribbon twisted pair cables. The ASICs outputs will be handled by LVDS differential receivers whose single ended output is then fed to modified FEC (skip the preamplifier stage) all relocated into minicrates outside the iron IRON

Front End for the BaBar IFR upgrade: option 3 (Angelo Cotta Ramusino) Each strip is equipped with a front end preamplifier based on one of the various amplifier/discriminator ASICs designed for HEP applications, with a passive adaptor to match its dynamic range to the IFR detectors’ one. The LVDS signals are locally converted to single ended LV-TTL and fed to a Field Programmable Gate Array (FPGA) which implements the storage and readout functions now performed by the monostables and the shift register of the FEC The ICB must provide the threshold voltage for the front end ASIC as well as the BaBar High Speed Clock needed by the FPGA. (not needed if the serial readout clock from the IFB is continuous because the FPGA can then recover a 4x clock from it by means of an internal PLL circuitry). One FPGA could replace one or more FECs Only the power and the serial CLOCK, SHIFT/LOAD and DATA lines must cross the iron boundary. COST and RADIATION HARDNESS are under evaluation. IRON

Front End for the BaBar IFR upgrade: option 3 Storage and output section of FPGA 16x INPUT STRETCHER Dual Port RAM 1024 * 16bit WritePtr ReadPtr OR 64 Shift Register 64x 1us window ~16us range 11us latency OR 64 Shift Register 64x Shift/Load Ck_Chain Data Out SHIFT REGISTER 16 x

Manpower At present:  USA: Princeton Univ., Ohio State Univ.?  INFN: Ferrara, Padova, other IFR groups Include more institutions to reach a reasonable size for the system ( especially needed for the installation, commissioning, operation)

Cost 13 planes with double-layer tubes  Cost about 510 K$ 10 planes with single-layer tubes + 3 planes with double-layer tubes  Cost about 340 KS We are working on a better estimate

Future R&D 16 tubes (options 2 and 3) have been ordered to Pol.Hi.Tec.  Test different configurations  Test with safe gas mixture  Test with BaBar IFR electronics

Tubes at Pol.Hi.Tech. View of the HV decoupling circuit

Tubes at Pol.Hi.Tech. View of the double layer end-cap

Pol.Hi.Tech. Large assembly hall available

Schedule Jan.15, 2003Decision Apr.15, 2003Order Jul.15, st tube Aug.15, 2003 Start assembling Jan.15, 2004Last tube Jul.1, 2004Start of installation of 2 sextants

Time scale for addressing issues Nov. 15, 2002  Preliminary results with double-layer prototypes  Preliminary estimation of electronic cost Dec. 14, 2002  Preliminary results with full size (4m) double-layer prototypes  Preliminary results of aging test (10mC/cm)  Conceptual design for assembling into modules  Conceptual design for installation  Decision on electronic options  Preliminary results of MC simulation with a real detector  Definition of QC procedure