1 Workshop Topics - Outline Workshop 1 - Introduction Workshop 2 - module instantiation Workshop 3 - Lexical conventions Workshop 4 - Value Logic System Workshop 5 - Data types A Workshop 6 - Data types B Workshop 7 - Operators Workshop 8 - Signed arithmetic Workshop 9 - Behavioral modeling A Workshop 10 - Behavioral modeling B Workshop 11 - Behavioral modeling C Workshop 12 - Data flow modeling Workshop 13 - Coding Styles

2 Loop Statements There are four types of loop statements: - while - for - repeat - forever The syntax for those loops is very similar to the syntax of loops in C programming All loop statements can appear only inside an initial or always blocks Loops may contain delay expressions

3 while loop The while loop executes until the while-expression is not true. If the loop is entered when the while-expression is not true, the loop is not executed at all. Syntax: ::= while ( ) The while statement should not be used to wait for a change in a value generated external to its always statement. The while-expression can have multiple conditions using operators Multiple statements should be grouped by begin-end

4 while loop example - counter module count_mod ; integer count ; initial begin count = 0 ; while (count < 128) // Execute loop till count is 127. Exit at count 128 begin $display ("Count = %d", count) ; / / $display System Task. Display string on STD output count = count + 1 ; end endmodule

5 A riddle How many times does the following while loop say Hello? initial begin a = 5 ; c = 0 ; while (a != c) begin $display("Hello") ; c = c + 1 ; end 5 times !!!

6 for loop The for loop contains three parts: - An initial condition - A check to see if the termination condition is true - A procedural assignment to change value of the control variable Initialization condition and the incremental procedural assignment are included in the for loop and do not need to be specified separately. Provides more compact loop structure than the while loop Can be executed at compile time. Used often in Test Benches Example: module counter ; integer count ; initial for (count = 0 ; count < 128 ; count = count + 1) $display("Count = %d", count) ; endmodule

7 for loop example – memory initialization Can be executed also within an always block. Example: memory load module mem_load ; reg[7:0] mem[0:15] ; // 16 bytes memory integer I, seed ; reg clk = 1’b0 ; always begin for (i = 0 ; i < 16 ; i = i + clk) // timed, clock synchronized load mem[i] = $random(seed) ; /*returns random 32bit signed integer. seed value (reg, integer or time variable) is optional */ end always #1 clk = ~clk ; initial #33 $finish ; endmodule

8 repeat loop The repeat loop is executed the given number of times. Cannot be used to loop on a general logic expression. The while loop is used for that purpose Must contain a number – constant, variable, signal value Syntax: repeat ( ) The value of the loop count is determined once at the beginning of the execution of the loop. Example: initial // Generate random data stimuli in Test Bench begin /* If number is a variable or a signal value, it is evaluated repeat (30) only when loop starts, not during loop execution */ (posedge clock) #1 data_in = $random ; // or $random(seed) end

9 forever Loop The forever loop does not contain any expression and executes forever until the $finish task is encountered Syntax: ::= forever A forever loop can be exited by the use of the disable statement. Example: // clock generation for Test Bench reg clock ; initial begin clock = 1'b0 ; forever #5 clock = ~clock ; // clock cycle time = 10 end initial #1000 $finish ;

10 Exiting Loops on Exceptional Conditions Any of the loop statements may be exited through use of the disable statement A disable statement terminates any named begin-end block and execution then begins with the statement following the block begin-end blocks may be named by placing the name of the block after a colon following the begin keyword: begin : break for (i = 0 ; i < n ; i = i + 1) begin : continue if (a == 0) disable continue ; // proceed with i = i if (a == b) disable break ; // exit for loop... end

11 Block types - Sequential and Parallel There are two Block types: Sequential and Parallel Block statements are used to group multiple statements to act together as one If a Sequential Block contains more than one statement, keywords begin and end are used to group the statements If a Parallel Block contains more than one statement, keywords fork and join are used to group the statements Fundamental difference between sequential and parallel blocks:  Statements in a Sequential Block are processed in the order they are specified  Statements in a Parallel Block are executed concurrently

12 Sequential Blocks Statements in a Sequential Block are processed in the order they are specified A statement is executed only after its preceding statement completes execution (except for non-blocking assignments) If delay or event control is specified it is relative to the simulation time, i.e. execution of the previous statement Example: // x =1, y=2, z=3 begin x = y * z ; // x = 6 y = x + 2 ;// y = 8 z = y – 1 ;// z = 7 end begin x = y * z ; // x completes at simulation time 0 #4 y = x + 2 ; // y completes at simulation time 4 #8 z = y – 1 ; // z completes at simulation time 12 end

13 Parallel Blocks All statements (or blocks) between a fork/join pair begin execution simultaneously upon execution flow hitting the fork Execution continues after the join upon completion of the longest running statement or block between the fork and join Makes the blocking assignments to become unblocking Order of statements is controlled by the delay or event control assigned to each statement If delay or event control is specified, it is relative to the time the block was entered fork - splitting a single flow into independent flows join - joining independent flows back into a single flow

14 Example - Parallel Block reg x, y ; reg [1:0] z, w ; initial fork x = 1'b0 ; // x completes at simulation time 0 #5 y = 1'b1 ; // y completes at simulation time 5 #10 z = {x, y} ; // z completes at simulation time 10 #20 w = {y, x} ; // w completes at simulation time 20 join

15 Frequently used System Tasks and Functions Standard tasks for routine operations. Used to generate input & output during simulation. Format: $ Synthesis tools parse and ignore system functions, hence they can be included even in synthesizable models. System tasks are always written inside procedures. Verilog output normally goes to the standard output and to the ‘verilog.log’ file. $display(“..”, arg2, arg3,.);$monitor($time, “..”, arg2, arg3,.); (similar to “printf” in C programming) $readmemh, $readmemb (" ",,, ) ; initialize the content of a memory array from a specified text file. text file must be in Hex format or Binary format. $finish ; terminates simulation when encountered

16 Exercise 3 Implement a multiplier with add and shift operators, using for loop. Make operands and result parametric. Start with 8bits operands. Load operands with load signal Read result when flag valid_data is on. Use positive clk edge event to synchronize add-shift iterations. Write a Test Bench for the multiplier. Design the same module using repeat loop.