Ultimate Device Scaling: Intrinsic Performance Comparisons of Carbon- based, InGaAs, and Si Field-effect Transistors for 5 nm Gate Length Mathieu Luisier 1, Mark Lundstrom 2, Dimitri Antoniadis 3, and Jeffrey Bokor 4 1 ETH Zurich, 2 Purdue University, 3 MIT, and 4 University of California at Berkeley

Motivation Simulation Approach Models and Validation General Scaling Considerations Band-to-band Tunneling Electrostatics and Contacts Source-to-drain Tunneling Performance Comparisons Conclusion and Outlook Outline

Motivation

Motivation: Future of Moore’s Law 65nm (2005) 45nm (2007) 32nm (2009) 22nm (2011) 5nm (2020) ?? Source: Intel Corporation 1.3-D Si FinFETs for ever? 2.What will be the dominant limiting factors when L g <10nm? Gate Length Reduction in planar Si MOSFETs: => increase of short-channel effects (SCE) => poor electrostatic control (single-gate) Gate Length Reduction in planar Si MOSFETs: => increase of short-channel effects (SCE) => poor electrostatic control (single-gate) => SOLUTION: 3-D FinFET since 2011

Leakage Sources in Ultrascaled Devices IBT/ S-to-D BTBT1 BTBT2 HIBL Band Diagram of L g =5nm Nano-transistor

How can we minimize leakage? Best device structure at L g =5nm: The least sensitive to leakage P. Hashemi et al., EDL 30, 401 (2009) L. Tapasztó et al., Nat. Nano. 3, 397 (2008) Y.Q. Wu et al., EDL 30, 700 (2009) NanowireGrapheneIII-V UTBCNT NEEDED: Fast, cheap, and reliable platform to investigate the performance of next-generation ultrascaled nano-transistors beyond 3-D FinFETs Supratik Guha, IBM Research

Simulation Approach

More Features Simulation Capabilities Efficient Parallel Computing 3D Quantum Transport Solver Different Flavors of Atomistic Tight-Binding Models Multi-Physics Modeling: From Ballistic to Dissipative (e-ph) Electron/Hole Transport Industrial-Strength Nano- electronic Device Simulator Multi-Geometry Capabilities Investigate Performance of Ultra-Scaled Nano-Devices before Fabrication Schrödinger-Poisson Solver with NEGF and WF Finite Element Poisson Accelerate Simulation Time through Massive and Multi- Level Parallelization 8Montag, 26. Oktober 2015 State-of-the-art Nano-TCAD Tool Physical Models Si Bandstructure TB: sp 3 d 5 s * OMEN Bias Momentum Energy Space

Model Verifications Expt: J. del MIT Expt: A. IBM YH Expt: S. RIT S. PSU III-V HEMT CNT FET BTBT Diode Zener Current NDR Current For more information, see presentation 23.7 by Aaron Franklin: “Sub-10 nm Carbon Nanotube Transistor”

General Scaling Considerations

Device Characteristics CNTNW SG-AGNR DG-AGNR DG-UTB

I d -V gs at V ds =0.5 V in Carbon Devices AGNR width: 2.1 nm / CNT diameter: 1.49 nm / Band Gap E g =0.56 eV Observations: same EOT gives very different electrostatic gate-channel coupling as long as E g >V ds, BTBT remains weak, but still intra-band tunneling SiO 2 EOT=0.64nm HfO 2 EOT=0.64nm BTBT HIBL/IBT

Intra-Band Tunneling: Electrostatics Spectral current through GAA CNT FETs with d=1.49 nm, E g =0.563 eV, different dielectrics, and EOT=0.64 nm Fringing Fields: stronger when spacer with large ε R effective channel length is longer same effect as gate underlap doping

Intra-Band Tunneling: Material (1) Fix electrostatic potential (Gaussian-like barrier) Investigate how semiconductor properties influence IBT CNT d=1nm E g =0.817eV Si NW d=3nm E g =1.404eV I d =4.4nA I d =91nA Smaller band gap (and m*) gives higher intra-band tunneling current Need to understand why OBSERVATIONS: Current flows through the potential barrier, almost no thermionic component

Intra-Band Tunneling: Material (2) What is needed: Under-the-Barrier (UB) model Same principle as Top-of-the-Barrier (ToB), but with Complex Bandstructure instead of Real Bandstructure Transmission through potential barrier: T(E)=exp(-2*Κ(E)*L) ToB UB E g =1.408eV E g =1.404eV E g =1.378eV E g =0.817eV

Ohmic vs Schottky Contacts Ohmic Schottky I d -V gs transfer characteristics for Si NW and CNT FETs with Ohmic and Schottky Contacts

Performance Comparisons

I d -V gs at V ds =0.5 V in CNT, NW, and UTB V DD =0.5 V Features: CNT with d=0.6nm and Si/InGaAs NW with d=3nm have same band gap: E g =1.4eV CNT with d=1nm has band gap: E g =0.82eV EOT=0.64nm made of 3.3nm HfO 2 No AGNR since worse than CNT Intrinsic characteristics d=1nm GAA-CNT (high IBT) and DG-UTB (bad electrostatics) scale poorly 3-D devices with same “large” band gap (E g =1.4 eV) scale better (low IBT) if CNT with d 1 eV possible, then at least as good as NW CHALLENGE: trade-off between high injection velocity (low m*) and low SS (high m*) needed, new constraint at short gate lengths

Conclusion

Conclusion and Outlook Simulation Platform for L g =5nm Ultra-scaled Devices Full-band and atomistic Same approximations for All Understand Limiting Factors Electrostatics and IBT Trade-off between v inj and SS Outlook Include non-ideal effects Try other crystal orientations Investigate nano-contact physics