PCI Target Interface Discussion: Using PCI-104 PCI Interface Development Solution Review June 15, 2006

PCI Local Bus Key Definitions PCI specification classifies two different AGENTS used in every PCI burst transfer: Initiator (Bus Master) Target (Addressed by the Initiator) Single Versus Multi-Function PCI Devices Each Function has its own Configuration Space Each Function Can Generate a Unique Interrupt Signal Naming Conventions “Low-Active” signal names are indicated with the use of the “#” symbol. 15-JUN-06 QUINTRON SYSTEMS

PCI Bus Details PCI Bus is unterminated - relies on Reflective Wave Switching Signal must be valid on the first reflected wave Detailed Electrical Spec to guarantee proper signal switching The PCI BUS does not use termination resistors. Since all bus transitions are based on CLK edge, the PCI BUS uses Reflective Wave Switching to assist the driven signal’s amplitude to prepare the signal transition to meet desired amplitude. The driver can be a lower current because the reflective wave will boost the signals state prior to rising edge of clock. At 33MHz the propagation delay (Tprop) is specified as 10ns (see specification for trace length, also review PCI104 since it really is a shorter bus). 15-JUN-06 QUINTRON SYSTEMS

Configuration Space (Rev 2.2) Each Function has a Configuration space is a 256-byte area inside each PCI device that contains information about the device. At power-up, the system scans the configuration space of all devices on the PCI bus and then assigns each device a unique base address and an interrupt level. The first 64 bytes (00h – 3Fh) make up the standard configuration header, predefined by the PCI spec, see adjacent figure. The remaining 192 bytes (40h – FFh) represent user-definable configuration space This region may store, for example, information specific to a PC card for use by its accompanying software driver PCI Data Structure The PCI Data Structure is in little-endian format and is in units of bytes. 15-JUN-06 QUINTRON SYSTEMS

Base Address Register (Memory) Base address Registers (BAR) allow an agent to be mapped dynamically into Memory Space 15-JUN-06 QUINTRON SYSTEMS

Base Address Register (I/O) Base address Registers (BAR) allow an agent to be mapped dynamically into I/O Space Not Recommended for New Designs. 15-JUN-06 QUINTRON SYSTEMS

Example Memory BAR 15-JUN-06 QUINTRON SYSTEMS

Command Bus C/BE#[3:0] Command Codes (no READ WRITE Pins) PCI uses Command Codes to indicate the type of bus transfer is occurring. There is no READ\WRITE pin, just a 4-bit bus used to define the transfer style the Host is issuing. 15-JUN-06 QUINTRON SYSTEMS

Byte Lanes: Local Byte Enables C/BE#[3:0] 32-Bit Burst Transfer 15-JUN-06 QUINTRON SYSTEMS

PCI Write Example (Burst of 4) 1) FRAME# Is asserted by the Initiator 2) Address Bus & Data Bus are Multiplexed. 3) Command is presented with Address, and latched by TARGETS on Rising Edge CLK-2 4) The Initiator transmits first data, along with appropriate BYTE Lanes (CLK-3) 5) Addressed Target responds with DEVSEL# (handshake) 6) When Target is ready to receive data it Asserts TRDY#, data will be written on Rising Edge of CLK-5 7) CLK-6 is the next data transfer (BURST) 8) CLK-7 is the next data transfer (BURST) 9) Initiator Rescinds IRDY# to indicate Final Data Phase is to Follow. 10) CLK-8 is the next (and final) data transfer phase of BURST. 11) Target Responds by Rescinding TRDY# & DEVSEL# signals 15-JUN-06 QUINTRON SYSTEMS

PC/104-Plus VS PCI-104 The PC/104-PLUS contains both: PC-104 ISA Bus A third connector opposite the ISA connectors supports the PCI bus (PCI-104 Form Factor). PCI-104 Interface (Proposed for Target) No ISA Bus Interface Strictly a 32-Bit PCI Interface 15-JUN-06 QUINTRON SYSTEMS

PCI-104 Board Stacking Design uses PCI-104 Non-Stackthrough Module (as shown to the right) No Support for ISA Interface (If PC/104-Pus SBC is used) 5 Boards Maximum, i.e. 1 Initiator and 4 Targets 15-JUN-06 QUINTRON SYSTEMS

PCI-104 Versus PCI Local Bus The PCI-104 bus connector is a 4x30 (120-pin) 2mm pitch stack-through connector as opposed to the 124-pin edge connector on standard 32-bit PCI. The 120-pin PCI-104 form factor does not support 64-bit Extensions, JTAG, PRSNT (Card Present), or CLKRUN signals. PCI-104 emulates the PCI Local Bus, using a stacking rugged form factor, to construct the bus (backplane). 15-JUN-06 QUINTRON SYSTEMS

PCI-104 Standards Based on PCI-104 Specification Version 1.0 (November 2003) PCI-104 Based on Revision 2.2 of PCI Local Bus Architecture Specification. Maximum CLK (supported) = 33MHz Maximum Data Bus Width = 32-bit Maximum Theoretical (Bursting) Data Transfer Rate = 132Mbytes Second 15-JUN-06 QUINTRON SYSTEMS

PCI Pin List 15-JUN-06 QUINTRON SYSTEMS The PCI bus has been simulated at 33MHz. For the purpose of this specification, 66MHz is not supported. To support future enhancements, the M66EN signal should be grounded on any module that cannot support 66MHz and left open for modules that can support a 66MHz clock. 15-JUN-06 QUINTRON SYSTEMS

PCI-104 120-Pin Bus Assignments IDSEL, CLK, INTx# are Distributed using separate Pins on connector. Host Boards implementing “5 volt PCI signaling” are not required to supply 3.3 volts to the modules, but must provide a bus and decoupling. Host Boards implementing “3.3 volt PCI signaling” are not required to supply 5 volts to the modules, but must provide a bus and decoupling. Trace Lengths Varies, depending on Agent’s position in the stack. IDSELx, Individual device select for configuration – one unique IDSEL line per agent. Signals Distributed using different lengths, Each Clock pin has a different length of trace on the HOST Agent, in order to accommodate Target distance in a stacked configuration. CLK0 is the longest trace on the HOST, and is assigned to first agent connected to the HOST. CLK1 is  0.662 less in length than CLK0 to accommodate the distance of two pins found on a third agent in a stack. 15-JUN-06 QUINTRON SYSTEMS

SOW Interface Requirements QUINTRON has provided the following requirements: Support 5.0/3.3V Signaling Explore IP CORE for FPGA versus dedicated Interface IC Support 32, 16, and 8-Bit bus widths facilitating linear addressing. TQFP Package (Avoid BGA – Not a Requirement) Research DMA & Bursting support. 15-JUN-06 QUINTRON SYSTEMS

Prototype Design Steps Research and propose Technology solution for Interface Design Design a Prototype to model a KEYSET based on PCI Target, meeting the following requirements: Memory-mapped access (8/16/32-bit) to devices, including: T1 Framer(s) (DS2155) 16 bit x 2K Dual-Port RAM 8/16-bit Read/Write registers 8-bit x 512 byte FIFO Breadboard space/expansion connector for add-on circuitry 15-JUN-06 QUINTRON SYSTEMS

Evaluation PCI-104 Block Diagram 15-JUN-06 QUINTRON SYSTEMS

Interface Design Technology Two Methods to develop Interface IP Core (Targeted FPGA must support 5.0V and 3.3V signaling), limited options. Use dedicated PCI Target Device, such as PLX9030 (verify life expectancy). 15-JUN-06 QUINTRON SYSTEMS

Intellectual Property Evaluation IP Core manufactures were evaluated based on the following guidelines: Support Older FPGA architectures to meet 5V interface requirement. Support TQFP FPGA (Non BGA Packages) Vendor’s Engineering Support Vendor Pricing for IP Core and Support 15-JUN-06 QUINTRON SYSTEMS

IP Core Manufactures Evaluated The Following is a List of Intellectual Property Core companies Evaluated: ALTERA (Free Core) Eureka PLDA 15-JUN-06 QUINTRON SYSTEMS

Review of ALTERA’s IP Core (Rejected) Currently IP core revision does not support older FPGA families, no 5V support (see adjacent table of Device Family Support Supports Low-Cost MAX II Family (No 5V). 15-JUN-06 QUINTRON SYSTEMS

Review of EUREKA Technologies EC125 PCI Target (Rejected) The default ALTERA family chosen by the IP Core was STRATIX (no 5V Support). DMA Support optional (Cost not researched see below). Retarget design to ACEX family, and the compiler fitted design into EP1K50FC256-1, which is a BGA package (family evaluation only, compile instantiate IP Core for evaluation only): Timing parameters not met in ACEX Family Poor Tech Support IP Core Price: $4,950 Maintenance service for the first year is 18% of the license fee ($891.00) 15-JUN-06 QUINTRON SYSTEMS

PLDA IP PCI-Target Core Evaluation PLDA is headquartered in France with a Sales Office in San Jose. Package included a Project setup wizard 15-JUN-06 QUINTRON SYSTEMS

PLDA Wizard 15-JUN-06 QUINTRON SYSTEMS

Sample Design Using PLDA Core 15-JUN-06 QUINTRON SYSTEMS

ALTERA 1K30 “Dual Function” Test Design Compiler Report 15-JUN-06 QUINTRON SYSTEMS

PLDA Evaluation IP Core Report PLDA qualifies as a solution, due to the following reasons: Support For ALTERA ACEX Family (5V) Tech Support was superb Configuration Tools work Very Well (Design Document was Not Linked By Installation Program). NO DMA Support (Software Engineering has decided DMA is not needed). Associated Pricing Price of the IP Core is $3290.00 Support is Included for First 6 Months ALTERA EP1K30QC208-1 (QUAN 500) = $30.50 ea 15-JUN-06 QUINTRON SYSTEMS

PLX 9030 Evaluation 3.3V, 5V Tolerant PCI Signaling PCI v2.2 compliant 32-bit 33MHz Target Interface Chip enabling PCI Burst Transfers up to 132Mbytes/second. Available in 176-pin PQFP (RoHS) Programmable 32-bit Local Bus Supports 5 PCI to Local Address spaces Four programmable Chip selects Nine Programmable GPIOs Big/Little Endian Conversion Interrupt Generator (Single INTA#) Two programmable FIFOs for zero wait state burst operation Host-SDK Windows Host Side Software Development Kit Available 15-JUN-06 QUINTRON SYSTEMS

PLX PCI9030 Target Application Direct Interface To PCI Bus Flexible Local Bus provides 32-bit Multiplexed or Non-Multiplexed Protocol for 8-, 16-, or 32-bit Peripheral and Memory devices 15-JUN-06 QUINTRON SYSTEMS

PLX9030 Architecture Flexible I/O Address Encoding for 8 or 16 Bit Data Buses using “Dynamic Data Bus Width Control Logic”. Lower Address Bits Derived from Byte Lanes 15-JUN-06 QUINTRON SYSTEMS

Byte Lanes: Local Byte Enables LBE[3:0] 16-Bit Transfer 15-JUN-06 QUINTRON SYSTEMS

Byte Lanes: Local Byte Enables LBE[3:0] 8-Bit Transfer 15-JUN-06 QUINTRON SYSTEMS

PLX9030 Synopsis & Availability Mature Product (Introduced in 1999) Used Throughout the Industry to interface Target Agents to PCI-32 Low Cost PCI9030A60PI F (F = RoHS) =$20.70 EA. (Quantities = 100) 12-13 WEEK Lead Time Hardware & Software Development Kits and Reference Designs Available 15-JUN-06 QUINTRON SYSTEMS

PCI-104 Review By: Robert Rappaport Presentation Available for download at: ftp.sierratech.net/pub/QUINTRON/