Device Characterization ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 1, 2004

Outline  NMOS Device Physics PMOS Device Physics PMOS Device Physics CMOS Inverter CMOS Inverter

MOSFET MOSFET = “Metal-Oxide-Semiconductor Field-Effect Transistor” Terminals:   G = gate   D = drain   S = source   B = body (substrate)

MOSFET Key Quantities Currents:   I G = 0 (due to insulating oxide layer)   I D   I S => since I G = 0, I D = I S (Kirchhoff’s Current Law) Voltages:   V G   V D   V S = 0 (usually)   V B = 0 (usually) Most important quantities: I D, V GS, V DS

MOSFET Cross-Section

Biasing 1) Source and substrate grounded (zero voltage) 2) (+) voltage on the gate   Attracts e - s to Si/SiO 2 interface   When threshold voltage (V GS = V Tn ) is reached, an inversion layer is formed 3) (+) voltage on the drain   e - s in the channel drift from source to drain   current flows from drain to source

I-V Characteristics I Dn vs. V GS : I Dn vs. V GS : V Tn = “threshold voltage” V Tn = “threshold voltage”  Voltage where Si/SiO 2 interface becomes strongly inverted with electrons  Voltage were NMOS transistor “turns on”

I-V Characteristics (cont.) I Dn vs. V DS : I Dn vs. V DS :

Linear Region Labeled “(1)” on previous plot Labeled “(1)” on previous plot I Dn = f(V GS, V DS ) and V DS < V GS – V Tn, V GS ≥ V Tn I Dn = f(V GS, V DS ) and V DS < V GS – V Tn, V GS ≥ V Tn Equation: Equation: where:  n = electron mobility in the channel, C ox =  ox /t ox, t ox = oxide thickness,  ox = oxide permittivity (3.9  0 for SiO 2 )

Saturation Region Labeled “(2)” on the previous plot Labeled “(2)” on the previous plot I Dnsat = f(V GS ) and V DS ≥ V GS – V Tn, V GS ≥ V Tn I Dnsat = f(V GS ) and V DS ≥ V GS – V Tn, V GS ≥ V Tn Equation: Equation:

Transconductance In the saturation region: In the saturation region: where: “Q” represents the quiescent operating point (i.e., fixed DC values of V GS, V DS )

Outline NMOS Device Physics NMOS Device Physics  PMOS Device Physics CMOS Inverter CMOS Inverter

Circuit Symbol

Cross-Section Appropriate I-V equations found by: 1) reversing the direction of I D 2) reversing the polarity of all bias voltages (V BS => V SB, V GS => V SG, V DS => V SD )

Biasing 1) Source and substrate grounded (zero voltage) 2) (-) voltage on the gate   Attracts h + s to Si/SiO 2 interface   When threshold voltage (V SG = -V Tp ) is reached, an inversion layer is formed 3) (-) voltage on the drain   h + s in the channel drift from source to drain   current flows from source to drain

Currents Linear: V SD ≤ V SG + V Tp, V SG ≥ -V Tp Linear: V SD ≤ V SG + V Tp, V SG ≥ -V Tp V SD ≥ V SG + V Tp, V SG ≥ -V Tp Saturation: V SD ≥ V SG + V Tp, V SG ≥ -V Tp

Transconductance In the saturation region: In the saturation region:

Outline NMOS Device Physics NMOS Device Physics PMOS Device Physics PMOS Device Physics  CMOS Inverter

Inverter Logic Logic symbol: Function: Truth table: AY 01 10

Ideal Voltage Transfer Characteristic V + = supply voltage V M = V + /2 = switching point of inverter (where input voltage = output voltage)

Actual Transfer Characteristic

Voltage Definitions V IL = input voltage where slope of transfer characteristic is -1 V IH = larger input voltage where slope of transfer characteristic is -1 V OH = output voltage at input voltage of V IL V OL = output voltage at input voltage of V IH V M = voltage where output voltage equals input voltage V MAX = output voltage when input voltage is zero (usually V MAX = V + ) V MIN = output voltage when input voltage is V + (usually V MIN ~ 0)

Voltage Definitions (cont.) V OH = minimum output voltage for valid logic 1 V OL = maximum output voltage for valid logic 0 V IH = minimum input voltage for valid logic 0 V IL = maximum input voltage for valid logic 1

Noise Margins Noise = unwanted variations in voltage which, if too great, can cause logic errors Noise margin high (N MH ): tolerable voltage range for which we interpret the inverter output as a logic 1 N MH = V OH – V IH Noise margin low (N ML ): tolerable voltage range for which we interpret the inverter output as a logic 0 N ML = V IL - V OL

Switch Representation

Switching Dynamics Input high: turn on bottom switch and discharge capacitive load   PMOS off   NMOS on (linear) Input low: turn on the top switch and charge capacitive load   PMOS on (linear)   NMOS off

VTC: Another Look (1) Input voltage = 0 V, output voltage = V DD (2) NMOS saturated, PMOS linear (3) Both transistors saturated (4) NMOS linear, PMOS saturated (5) Input voltage = V DD, output voltage = 0 V

Approximate VTC V OH = V MAX ; V OL = V MIN V M is input voltage where V OUT =V IN = V M

Currents NMOS current at V IN = V M is: PMOS current at V IN = V M is:

Deriving V M Define: Define: and and Setting I Dn = -I Dp gives: Setting I Dn = -I Dp gives:

Computing Noise Margins To compute noise margins, the next step is to calculate V IL and V IH Do so by determining the slope of the transfer characteristic at V IN = V M (i.e., voltage gain) Then:   Project a line to intersect at V OUT = V MIN = 0 V to find V IH   Project a line to intersect at V OUT = V MAX = V DD to find V IL

Voltage Gain Voltage gain can be shown to be: where: r on and r op are output resistances of the NMOS and PMOS transistors, respectively   In general: and   We can find r o by inverting the slope of the I D vs. V DS characteristic

Noise Margins We can find V IL and V IH using the slope (A v ) of the VTC: Noise margins: