CprE / ComS 583 Reconfigurable Computing Prof. Joseph Zambreno Department of Electrical and Computer Engineering Iowa State University Lecture #10 – HW #2 / Projects Discussion

Lect-10.2CprE 583 – Reconfigurable ComputingSeptember 20, 2007 Recap – Introduction to Cryptography Encryption is the process of encoding a message such that its meaning is not obvious Decryption is the reverse process, i.e., transforming an encrypted message to its original form We denote plaintext by P and ciphertext by C C = E(P), P = D(C) and P = D(E(P)), where E() is the encryption function (algorithm) and D() the decryption function EncryptionDecryption Plaintext Ciphertext

Lect-10.3CprE 583 – Reconfigurable ComputingSeptember 20, 2007 Signing With Message Digests A message digest (or hash) function is a one-way function which produces a fixed length vector of an input block x of arbitrary length A fixed length “fingerprint” of a message Instead of signing message, sign the message digest m HE || Private Key H Compare D Public Key E(H(m)) m

Lect-10.4CprE 583 – Reconfigurable ComputingSeptember 20, Gbps SHA-512 Implementation Partial unrolling (5 rounds), pipelining 1 Gbps on Virtex-E FPGAs See [LieGre04A] for details

Lect-10.5CprE 583 – Reconfigurable ComputingSeptember 20, 2007 Application – Private-Key Crypto The Advanced Encryption Standard (AES) is becoming the block cipher of choice for private-key cryptography Implementing AES on FPGA hardware has been looked at in some depth: Approximately 50 unique research implementations! Various commercial cores (Actel, Helion Tech, Amphion, etc.) Approach taken – an exploration of the decisions that lead to area/delay tradeoffs in an AES FPGA implementation End result – pareto optimal designs in terms of throughput, latency, and area efficiency

Lect-10.6CprE 583 – Reconfigurable ComputingSeptember 20, 2007 AES-128E Algorithm 128-bit plaintext 128-bit key Round Transformation round++ round = 10? SubBytes ShiftRows AddRoundKey 128-bit ciphertext Yes No KeyExpansion MixColumns

Lect-10.7CprE 583 – Reconfigurable ComputingSeptember 20, 2007 Input plaintext R1R1 Output Ciphertext R2R2 R3R3 R4R4 R5R5 R6R6 R7R7 R8R8 R9R9 R 10 Results: UF10-PP3D SubBytesShiftRowsMixColumns KeyExpansion AddRoundKey

Lect-10.8CprE 583 – Reconfigurable ComputingSeptember 20, 2007 Application – Random Number Generation Cryptographic applications often require good sources of random numbers: Key generation Initialization vectors Types of random number generators: Pseudo-Random Number Generators (PRNG) – appear to be random, initialized with an externally generated sequence (deterministic) Cryptographically Secure PRNGs (CSPRNG) – a PRNG where prediction of the next input bit given a previously- generated sequence is computationally intractable True Random Number Generators (TRNG) – output is based on some underlying physical random process

Lect-10.9CprE 583 – Reconfigurable ComputingSeptember 20, 2007 The Method [KohGaj04A] Make use of the clock jitter in a circuit: Variation of the significant instants of the clock Nondeterministic, may have many sources: Semiconductor noise Crosstalk Power supply variations Electro-magnetic fields

Lect-10.10CprE 583 – Reconfigurable ComputingSeptember 20, 2007 Overall Design

Lect-10.11CprE 583 – Reconfigurable ComputingSeptember 20, 2007 Ring Oscillators Uses Propagation Delay – 130 MHz

Lect-10.12CprE 583 – Reconfigurable ComputingSeptember 20, 2007 Sampler Circuit One of the clock signals is used to sample the other signal

Lect-10.13CprE 583 – Reconfigurable ComputingSeptember 20, 2007 Sampler Output Clock Skew (jitter) in between two clock signals is used (e.g. sampled) to generate a totally random bit The output clock skew: Will never be uniform Is not simple out-out-phase behavior

Lect-10.14CprE 583 – Reconfigurable ComputingSeptember 20, 2007 Good Speed Ratios Ring oscillators with closely matched frequencies require that a desired speed ratio must be achieved What factors affect this achievement? Variation in CLB speed 7% difference between the slowest CLB and the fastest one Sensitive to temperature and difficult for measurement Variation in the frequency of an oscillator with the chip temperature Close placement To use a large number of oscillators

Lect-10.15CprE 583 – Reconfigurable ComputingSeptember 20, 2007 CLB Speed / Temperature Variation

Lect-10.16CprE 583 – Reconfigurable ComputingSeptember 20, 2007 Summary FPGA platforms are a popular choice for implementing cryptographic applications High throughputs Relatively low design cost Algorithmic agility / upload Many other algorithms have been implemented that we haven’t discussed today: Public-key cryptography (e.g. RSA, ECC) Private-key cryptography (e.g. DES, 3DES) Cryptographic hash functions (e.g. MD5, RIPEMD) Security issues as they pertain to using FPGAs have not been fully addressed

Lect-10.17CprE 583 – Reconfigurable ComputingSeptember 20, 2007 Project Proposals Due Sunday, 9/30 at midnight Purpose – to provide a background and overview of the project Goal – allow me to understand what you are intending to do Project topic: Perform an in-depth exploration of some area of reconfigurable computing Whatever topic you choose, you must include a strong experimental element in your project Work in groups of 2+ (3 if very lofty proposal)

Lect-10.18CprE 583 – Reconfigurable ComputingSeptember 20, 2007 Some Suggested Topics Design and implementation of X Pick any application or application domain Identify whatever objectives need to optimized (power, performance, area, etc.) Design and implement X targeting an FPGA Compare to microprocessor-based implementation Network processing Explore the use of an FPGA as a network processor that can support flexibility in protocol through reconfiguration Flexibility could be with respect to optimization Could provide additional processing to packets/connections Implement a full-fledged FPGA-based embedded system From block diagram to physical hardware Examples: Image/video processor Digital picture frame Digital clock (w/video) Sound effects processor Any old-school video game Voice-over-IP

Lect-10.19CprE 583 – Reconfigurable ComputingSeptember 20, 2007 Suggested Project Topics (cont.) Prototype some microarchitectural concept using FPGA See proceedings of MICRO/ISCA/HPCA/ASPLOS from last 5 years Survey some recurring topic Compare results from simulation (Simplescalar) to FPGA prototype results Evaluation of various FPGA automation tools and methodologies Survey 3-4 different available FPGA design tools Pick a representative (pre-existing) benchmark set, see how they fare…how well do they work? Analyze output designs to determine basic differences in algorithms and methodology Anything else that interests you!

Lect-10.20CprE 583 – Reconfigurable ComputingSeptember 20, 2007 Previous Year’s Topics Fall 2006 projects: “FPGA Implementation of Frequency-Domain Audio Filter Bank” (2 students) “Transparent FPGA-Based Network Analyzer” (2 students) “FPGA-Based Library Design for Linear Algebra Applications” (2 students) “An Improved Approach of Configuration Compression for FPGA-based Embedded Systems” (2 students) “Analysis of Sobel Edge Detection Implementations” (1 student) “Artificial Neural Networks on Dynamically Reconfigurable FPGAs” (3 students) Papers and presentations for these are available upon request We can do better!

Lect-10.21CprE 583 – Reconfigurable ComputingSeptember 20, 2007 Proposal Structure Suggested structure [3-4 pages, IEEE conf. format] Introduction – what is the context for this work? What problem are you trying to address? Why is it interesting/challenging? Prior work – what is the related work? How does your work differ from these? (5-10 references) Approach – how are you going to tackle the problem? What tools and methodologies do you intend on using? What experiments do you intend on running? Expected results – what do you expect the outcome of your project to be? What are the deliverables? How do you intend on presenting your results? Milestones – what is your expected progress schedule? Provide a weekly / bi-weekly basis