Distributed computing using Projective Geometry: Decoding of Error correcting codes Nachiket Gajare, Hrishikesh Sharma and Prof. Sachin Patkar IIT Bombay 13/02/09

Background  Projective Geometry : Derived from extension of a Galois field of a prime order p to a vector space of higher dimension  Useful properties of incidence and symmetry between subspaces of the geometry  Applications : Distributed computing, Encoding and decoding of error correcting codes

Applications to distributed computing  Karmarkar’s perfect access patterns for multiple processors and memories  Interconnections between processors and memories based on connections of a projective geometry  A schedule of memory accesses per processor such that there are no access collisions  Such a schedule is generated due to the property of automorphisms in the geometry  Use of PG as a general computational model for part/whole of computations

Area of current research  Linear block codes based on Projective Geometry  Low density Parity Check (LDPC) codes and Expander codes  Decoding of block PG-LDPC codes using Karmarkar’s perfect access patterns  Evaluation of the architecture on a Xilinx Virtex-V FPGA  Architecture proposed by Hrishikesh Sharma

LDPC codes  k code bits, n-k parity bits involved in n-k parity check equations involving the code bits  Low no. of bits per parity check  Code represented by a bipartite Tanner graph

Decoding of LDPC codes  Finding the most probable codeword that could have been sent, given the received word  Messages passed along the edge of the Tanner graph, representing the belief about the value of the node/parity of the check equation  Each type of node in the bipartite graph arithmetically compute the messages, in parallel synchronization with each other  Decoding ends when all the constraints are met

Decoder Specifications on the FPGA  114 Processing Elements for decoding a code based on a 2-dimensional projective geometry over GF(7)  An upper limit of 150 PE’s on the best FPGA from Xilinx  Classical Belief Propagation algorithm in the logarithmic domain  114 True Dual port Block RAM’s used as memory elements  Initial study on decoding a block of 57 bits and evaluating the performance of the PG interconnect

Decoder features  Use of optimized data representation width for maximizing the code performance over a noisy channel  Multiple memory accesses in one cycle possible due to Karmarkar’s perfect access schedule  Decoding expected to be faster due to higher girth of PG-codes  Deterministic nature of the decoding algorithm on the architecture simplifies the control logic  Expected run time complexity of approximately 25 clock cycles per iteration

Current Status of work  Processing Elements designed and implemented  Memory modules as IP Block RAM cores from Xilinx CoreGen  Other arithmetic cores customized and implemented using Xilinx CoreGen  Sequential addressing scheme used for memory access  Simulation planning ongoing

Proposed Evaluation  Functional correctness and performance of the perfect access patterns  Expected to perform better than CPU based decoders  Verification of a computational schedule folded on a smaller no. of PE’s  Throughput of the decoder to match the requirements in areas like magnetic storage systems  Focus on ASIC design  To provide the required performance for practical applications  To achieve the scalability for larger codes