KeyStone II Interrupts. Agenda Motivation for this presentation The interrupt Scheme – SPI 0 example Configure interrupt - Hyperlink example.

Slides:



Advertisements
Similar presentations
purpose Search : automation methods for device driver development in IP-based embedded systems in order to achieve high reliability, productivity, reusability.
Advertisements

Yaron Doweck Yael Einziger Supervisor: Mike Sumszyk Spring 2011 Semester Project.
Concept V2.5 Lesson 11 Objectives: After completing this lesson, the learner will be able to:  Define the configuration rules associated with the Quantum.
Corporate Property Automated Information System (CPAIS) Macro Walkthrough Guide for Excel Version 2003.
FIU Chapter 7: Input/Output Jerome Crooks Panyawat Chiamprasert
EET 450 Chapter 2 – How hardware and Software Work Together.
University College Cork IRELAND Hardware Concepts An understanding of computer hardware is a vital prerequisite for the study of operating systems.
KeyStone Training Multicore Applications Literature Number: SPRPXXX
Functional Simulation Overview1 OpenTV PC Simulator.
Dr. Kimberly E. Newman Hybrid Embedded wk3 Fall 2009.
EZ Positioning with SINAMICS S120 Agenda
Installing software on personal computer
MSP432™ MCUs Training Part 9: Porting between MSP430 and MSP432
On a Device Information Model for devices in oneM2M
ShelterPoint™ Data-Entry Workflows. ShelterPoint v5.2.3.
ECE 265 – LECTURE 12 The Hardware Interface 8/22/ ECE265.
KeyStone Resource Manager June What is resource manager? LLD for global Resource management – static assignment of the device resources to DSP cores.
SOC Consortium Course Material SoC Design Laboratory Lab 8 Real-time OS - 2 Speaker: Yung-Chih Chen Advisor: Prof. Chun-Yao Wang November 17, 2003 Department.
EE 446 Project Assignment Top Design Sensor Components Pin Assignment and Configuration Completed Physical Setup Project Tasks.
Typical Microcontroller Purposes
CHAPTER 3 TOP LEVEL VIEW OF COMPUTER FUNCTION AND INTERCONNECTION
8086 has 2 interrupt inputs 1. NMI 2. INTR For application where we have interrupts from multiple sources, use an external device called a Priority Interrupt.
Lecture 3. APIC ID Prof. Taeweon Suh Computer Science Education Korea University COM509 Computer Systems.
2009 Sep 10SYSC Dept. Systems and Computer Engineering, Carleton University F09. SYSC2001-Ch7.ppt 1 Chapter 7 Input/Output 7.1 External Devices 7.2.
Dr Mohamed Menacer College of Computer Science and Engineering Taibah University CE-321: Computer.
Challenges in KeyStone Workshop Getting Ready for Hawking, Moonshot and Edison.
Keystone Family PCIE Eric Ding. TI Information – Selective Disclosure Agenda PCIE Overview Address Translation Configuration PCIE boot demo.
EEE440 Computer Architecture
6-1 Infineon 167 Interrupts The C167CS provides 56 separate interrupt sources that may be assigned to 16 priority levels. The C167CS uses a vectored interrupt.
EDMA3, QDMA and IDMA for the Keystone Platform
Msi interrupt reception as EP. Msi debug Based on sprugs6a.pdf, Keystone architecture Perpheral Component Interconnect Express (PCIe) wrote 8 into MSI_IRQ.
Debugging TI RTOS TEAM 4 JORGE JIMENEZ JHONY MEDRANO ALBIEN FEZGA.
DSP/BIOS for C6000/C5000. What is DSP/BIOS Real-time Environment –Thread execution model Threads, Mailboxes, Semaphores –Device independent I/O Logging,
Chapter 5 - Interrupts.
Input/Output Problems Wide variety of peripherals —Delivering different amounts of data —At different speeds —In different formats All slower than CPU.
Linux Operations and Administration
DSP C5000 Chapter 10 Understanding and Programming the Host Port Interface (EHPI) Copyright © 2003 Texas Instruments. All rights reserved.
Unity Application Generator Step 4d: Defining PLC.
Collaborate. Coordinate. Evaluate. Connecting Communities > Demonstrating Outcomes ™ / I&R Housing Youth & Family Services Older Adult Services ShelterPoint™
How to setup DSS V6 iSCSI Failover with XenServer using Multipath Software Version: DSS ver up55 Presentation updated: February 2011.
CSL DAT Adapter CSL 2.x DAT Reference Implementation on EDMA3 hardware using EDMA3 Low level driver.
Lab 1: Using NIOS II processor for code execution on FPGA
Microprocessor and Assembly Language
Code review: GPIO, timer, and ISR
Microprocessor Systems Design I
After Mcasp_open completed
Key Terms By: Kelly, Jackson, & Merle
The PCI bus (Peripheral Component Interconnect ) is the most commonly used peripheral bus on desktops and bigger computers. higher-level bus architectures.
8259 Chip The Intel 8259 is a family of Programmable Interrupt Controllers (PIC) designed and developed for use with the Intel 8085 and Intel 8086 microprocessors.
Installing the HI 6600 into the CompactLogix System.
OSKAR station simulator
Peripheral Devices
Training Module Introduction to the TB9100/P25 CG/P25 TAG Customer Service Software (CSS) Describes Release 3.95 for Trunked TB9100 and P25 TAG Release.
5 × 7 = × 7 = 70 9 × 7 = CONNECTIONS IN 7 × TABLE
How to Submit Google Docs to the Homework Drop Box
5 × 8 = 40 4 × 8 = 32 9 × 8 = CONNECTIONS IN 8 × TABLE
4 × 6 = 24 8 × 6 = 48 7 × 6 = CONNECTIONS IN 6 × TABLE
5 × 6 = 30 2 × 6 = 12 7 × 6 = CONNECTIONS IN 6 × TABLE
10 × 8 = 80 5 × 8 = 40 6 × 8 = CONNECTIONS IN 8 × TABLE MULTIPLICATION.
3 × 12 = 36 6 × 12 = 72 7 × 12 = CONNECTIONS IN 12 × TABLE
Post Lab Quiz 3 Review Assignment 2 Help
Certification Individual Report
5 × 12 = × 12 = × 12 = CONNECTIONS IN 12 × TABLE MULTIPLICATION.
Entering Material Factors
KeyStone Training Multicore Applications Literature Number: SPRPXXX
Microprocessor and Assembly Language
5 × 9 = 45 6 × 9 = 54 7 × 9 = CONNECTIONS IN 9 × TABLE
Certification Individual Report
3 × 7 = 21 6 × 7 = 42 7 × 7 = CONNECTIONS IN 7 × TABLE
Presentation transcript:

KeyStone II Interrupts

Agenda Motivation for this presentation The interrupt Scheme – SPI 0 example Configure interrupt - Hyperlink example

Configuring an Hwi: Statically via GUI 1 Use Hwi module (Available Products), insert new Hwi (Outline View) Example: Tie SPI_INT to the CPU HWI 5 2 Configure Hwi: Event ID, CPU Int #, ISR vector: To enable INT at startup, check the box Where do you find the Event Id #? NOTE: BIOS objects can be created via the GUI, script code, or C code (dynamic).

Hardware Event IDs  How do you know the names of the interrupt events and their corresponding event numbers? Look it up in the datasheet. Source: TMS320C6678 datasheet  As appropriate, refer to the datasheet for your target platform. What happens in the ISR ?

Agenda Motivation for this presentation The interrupt Scheme – SPI 0 example Configure interrupt - Hyperlink example

System Events

System Events Some events are connected directly to Cores But not SPI

C66 Event Mapping Table 9-2 in the C66 UG 1.22 assigned events (5 reserve primary events, 17 secondary events) 2.7 reserved events 3.99 Available events 4.The available events are connected to the Device. The next slides will show how and what is connected to the available events in the 6638 device.

C6638 Interrupt Topology Table 5-4 in the 66AK2H12 1.All events from all IP come to the interrupt controllers 2.Some are connected directly to C66 or other masters (EDMA, ARM, Hyperlink) and some are mapped by the interrupt controllers

Where is SPIXEVT? Not on the above page Not on any of the other two pages in the table But we see that there are eight events (56 to 63) that come out of the interrupt controller. We can connect SPIXEVT through the interrupt controller to one of these events (broadcast events). We will connect to broadcast event 63 They are other events from the interrupt controller that could be considered (Both, broadcast and single core) The ARM GIC has 480 input events and 12 of them are connected to SPI

Connecting SPIXEVT to Core 3 66AK2H12 has multiple instances of SPI, we will look at SPI 0 The next slide will show one page from the input table for CIC0. Same events are connected to CIC1 as well

Connecting SPI 0 Transmit event to core 3 ISR

Agenda Motivation for this presentation The interrupt Scheme – SPI 0 example Configure interrupt – Hyperlink example

Configuration API Read the following Wiki: For KeyStone II (MCSDK 3), look at the two include files csl_cpIntc.h and csl_cpIntCAux.h to see all the API that are needed The next slide with show APIs to connect system events to channels (output of the CIC) Connect the channel events to interrupt line is done using CSL or SYSBIOS as described in the beginning of the presentation (but with the correct C66 event number)

Code examples Examples in the release MCSDK_3_01_12\pdk_keystone2_3_00_01_12\pack ages\ti\drv there are examples that use interrupts from peripherals We will look at HyperLink example The example – getting an interrupt from Hyperlink 0 to a core

Hyperlink UG

Following Hyperlink Interrupt 0 From table 5-24 of 66AK2H12- CIC0 input events Event number 111 (ox6F) is HyperLink 0 interrupt Next we have to connect this to a core

static int hyplnkExampleInitChipIntc (void) { CSL_CPINTC_Handle hnd; // I drop some of the functions here (enable/disable interrupts etc. CSL_CPINTC_mapSystemIntrToChannel (hnd, CSL_CIC0_HYPERLINK_0_INT, hyplnk_EXAMPLE_INTC_OUTPUT); // I drop some of the functions here (enable/disable interrupts etc. return 0; } CSL_CIC0_HYPERLINK_0_INT = 111 What about hyplnk_EXAMPLE_INTC_OUTPUT?

Choose to use event 45 of the core It could be any one of other CIC_OUT lines (look at the complete table for even more)

Following Hyperlink Interrupt 0 - Continue Event 45 on the C66 core is connected to CIC out x N, that is – Core 0 event 45 is connected to CIC output event 64 – Core 1 event 45 is connected to CIC output event 74 – Core 2 event 45 is connected to CIC output event 84 – You got the point CIC0 should map input event 111 to output event 64 (or 74, or 84 or … depends on what core is used)

Screen Shot of CCS The value of hyplnk_EXAMPLE_INTC_OUTPUT is ( * DNUM)

Questions?