1 LLRF Pre-readiness review (26th May, 2009) 27/10/2015 LLRF performance and its limitation based on KEK's experiments Shin Michizono (KEK) KEK’s LLRF performance Noise analysis Improvements by averaging (or filtering) Algorithm 8/9pi mode Summary

LLRF Pre-readiness review (26th May, 2009) 2 RF 4 vector sum control 0.007%rms 0.018deg.rms 0.01%rms 0.02deg.rms in case of single cavity feedback The performance is similar between 4-vectorsum and single cavity. We analyzed the limitation of the performance 27/10/2015

LLRF Pre-readiness review (26th May, 2009) 3 Possible noise sources [LLRF hardware/software dependent] 1.Digital noise at ADC/FPGA -> Clean 10 MHz input -> Feedback algorithm 2.Phase noise at LO signal (phase jitter) -> Phase noise measurement 3.Clock jitter at ADC -> Phase noise measurement 4. Harmonics at downconverter -> Spectrum measurement [Cavity dependent] 1. 8/9pi, 7/9pi modes elimination 27/10/2015

LLRF Pre-readiness review (26th May, 2009) 4 Clean 10 MHz or downconverted signals were measured at our digital system. ADC data acquisition and FFT analysis Bench test of cPCI system Amplitude [%] Phase [mdeg.] STF 4 vector sum7.00E-0320 single cav.1.00E-0320 clean 10 MHz7.00E-035 Mixer 10 MHz1.50E-0212 FFT spectrum at cPCI (input: clean 10 MHz) -> No spurious observed Phase error is better at clean 10 MHz input. (noise source would be LO or Mixer ）

27/10/2015 LLRF Pre-readiness review (26th May, 2009) 5 Digital filter (averaging) Digital low-pass filter is quite effective to improve the signal noise ratio. (M)

27/10/2015 LLRF Pre-readiness review (26th May, 2009) 6 Jitter (10 Hz-1 MHz) is 0.5 m degree. Phase noise measurement [mdeg.] 10MHz0.58 Mixer 10MHz MHz CLK1.81* MO1300MHz16.09 LO1310MHz18.11 *jitter in 10 MHz Jitter (10 Hz-1 MHz) is calculated. Higher jitter of LO would be the dominant factor of the phase error.

27/10/2015 LLRF Pre-readiness review (26th May, 2009) 7 without LPF -56dBc (2 nd ), -66dBc(3 rd Harmonics of downconverter with LPF -73dBc (2 nd ), <-75dBc(3 rd Due to non-linearity, 2 nd and 3 rd should be supperessed <-60dBc.

1.3GHz 1.3GHz+250kHz +1.3GHz (Leakage from LO generator) 0kHz (ADC offset, DC comp. by leakage from LO), 250kHz (IF), 500kHz (2 nd harmonics of IF), … FPGA algorithm (example:250 kHz IF) 27/10/ LLRF Pre-readiness review (26th May, 2009) These errors can be eliminated by the definition of I/Q comp. I’ = ( I - (-I) )/2 Q’ = ( Q - (-Q) )/2 (J-PARC and STF adopted this procedure.)

Feedback-instability due to 8/9  and 7/9  modes L.O. Klystron 400kW AMP. IQ Modulator M. O. ADC DAC I Q LPF (fc=0.4MHz) FPGA 9cell cavity remove LPF A digital delay system (  s/clock) was implemented in the FPGA in order to observe the relation between feedback loop delay and instability. LPF was removed in order to allow other passband modes pass through. FB loop delay was changed using digital delay. Additional delay:1 clock ~ 120 clock(3  s) 9 LLRF Pre-readiness review (26th May, 2009)

Intensities of 8/9 , 7/9  and 6/9  Modes Vec.sum cav4 cav3 cav2 cav1 In the case of P-Gain~55 Additional Delay Time (  s) Stable region is extremely narrow. Stable positions are different from each cavity because of different mode frequencies. by superposition In the case of vectorsum operation, FB control is unstable for all delay time. 27/10/ LLRF Pre-readiness review (26th May, 2009) unstable stable

27/10/2015 LLRF Pre-readiness review (26th May, 2009) 11 KEK’s cavity performance was verified. Phase error (0.02deg. compared with 0.07% in amplitude) comes from the rf signal jitter. The largest part of noises comes from LO jitter. Due to the synchronized noises between 4 cavity pickups, phase errors are almost same even after 4 cavity vector sum. Averaging (digital filter) improves such phase jitter. Harmonics of the mixer should be considered when high stability operation. 8/9pi, 7/9pi instabilities are enhanced at high gain operation. Summary

27/10/2015 LLRF Pre-readiness review (26th May, 2009) 12

Cavity fields and their frequency spectra IF (  mode) 7/9  6/9    8/9  Stable Case : Digital Delay =1clock (0.025  s) Unstable Case : Digital Delay =5clock (0.12  s) Unstable Case : Digital Delay=23clock (0.57  s) cavity Examples of the results for different delay In unstable case, 8/9 , 7/9 , and 6/9  modes were observed. 27/10/ LLRF Pre-readiness review (26th May, 2009)